I wrote a simple counter in VHDL for a program counter. Everything is done in a process, but what I dont understand is that in the simulation, the addition of the program counter, is only done at the next clock event, rather than immediately after PCNext has been output.

Here is the code as well as the simulation:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY dlatch IS PORT (
     Reset, Clock : IN std_logic;
     PC_out : OUT std_logic_vector(31 downto 0));
end;

ARCHITECTURE d_arch OF dlatch IS

  SIGNAL PC      : std_logic_vector(31 downto 0);  
  SIGNAL PCNext  : std_logic_vector(31 downto 0);  
BEGIN 
  PROCESS(Clock, Reset)  
    BEGIN 
 
IF Reset = '1' THEN
    PC <= x"00000000";
    cycle := 0;
ELSIF Clock'event and Clock = '1' THEN
    cycle := cycle+1;
    PC <= PCNext;
    
ELSE
END IF;

PCNext <= std_logic_vector(unsigned(PC) + 4); 

END PROCESS ;

 PC_out <= PC;
END d_arch;

Do you see how PCNext is only calculated at the falling edge of the clock? Why isn't it calculated immediately after PC <= PCNext  ?

I wrote a simple counter in VHDL for a program counter. Everything is done in a process, but what I dont understand is that in the simulation, the addition of the program counter, is only done at the next clock event, rather than immediately after PCNext has been output.

Here is the code as well as the simulation:

 LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    
    ENTITY dlatch IS 
    PORT (
         Reset, Clock : IN std_logic;
         PC_out : OUT std_logic_vector(31 downto 0)
         );
    end dlatch;
    
    ARCHITECTURE d_arch OF dlatch IS
    
    SIGNAL PC      : std_logic_vector(31 downto 0);  
    SIGNAL PCNext  : std_logic_vector(31 downto 0);  
    
    BEGIN 
    PROCESS(Clock, Reset)  
    BEGIN 
         IF Reset = '1' THEN
              PC <= x"00000000";
         ELSIF Clock'event and Clock = '1' THEN
                PC <= PCNext;
         END IF;
    
        PCNext <= std_logic_vector(unsigned(PC) + 4); 
        
    END PROCESS;
    
    PC_out <= PC;
    
    END d_arch;

Do you see how PCNext is only calculated at the falling edge of the clock? Why isn't it calculated immediately after PC <= PCNext?