Questions tagged [mips]

MIPS is a reduced instruction set computer (RISC) architecture that has both 32 and 64-bit variants. The technology is often licensed as IP cores to manufacturers. The Microchip PIC32 series is an example of a common microcontroller based on the MIPS M4K core and several FPGAs include a MIPS microprocessor.

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MIPS clock cycle calculation formula

How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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Devices storing volatile memory

I've hit a bit of a rut in a question on my homework for my computer architecture class (MIPS architecture): what are digital logic devices that can implement 1 bit and 32 bit volatile memory, and ...
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Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 ...
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173 views

How is the lh (load halfword) instruction implemented in MIPS?

I am a bit confused about lh (load halfword) instruction. Would it be correct to say that it gets the contents of the address just like in load word instruction but then takes the 16 rightmost bits ...
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Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
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MIPS Help (Modulo or Something Similar)

I have this project in MIPS and I read in user input of 10 integers into an array of length 10. After reading them I need to iterate through the array and add the odd numbers (not odd numbered ...
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79 views

The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
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Can't understand what multiplexers do in CPU datapath

I'm currently learning about data path in a CPU and having a hard time understanding the functionality of G,L, H parts in the following image. Why have those parts been used there?Thanks in advance.
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MIPS invert - why are the 2 operands always inverted first thing?

I'm learning about MIPS 32 bit. I understand that CMOS technology uses NAND and NOR for the AND and OR commands, but still, I don't understand why is the inverter at the begining. Another thing is ...
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Verilog Reg File: Cant mix blocking and non-blocking assigment

I want to implement a blocking read to read the data as soon as it is written. I am trying to implement a MIPS 1 pipeline and i need the data to be available in the same clock it is written. The flips ...
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Store Word variation in MIPS 32

How can I implement a variant of the SW (store word) that would do basically the same as the SW statement, however that would do a duplicate writing of a word in two consecutive memory addresses? For ...
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Finding speedup in instruction pipeline with branch prediction

I was solving below exercise problem from book Computer Architecture and Design by Patterson at al. This could be more mathematical / logical doubt than electronics related doubt. Breakdown of ...
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Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
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Finding speedup when branch prediction is done in instruction decode phase of processor pipeline instead of execute stage

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Assume instructions: ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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How many stall cycles resulted by incorrectly predicted branch in instruction pipelining

I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy: The importance of having a good branch predictor depends on how often conditional branches ...
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59 views

Why does 1-bit predictor miss on first iteration of inner loop next time around?

My computer organization and architecture claims that with 1-bit predictor, there are 2 mispredicts. The first miss is when mistaken on last iteration of inner loop. The second one is as not taken ...
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194 views

Overflow detection and efficiency

I know the add instruction in mips32 will do overflow detection, i.e. add $t0, $s0, $s1; I want to know whether this feature ...
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Why does a divider needs 1 more step?

My book introduces a divider design: It said that if the divisor is n-length number, we need n+1 steps to finish the division. For example: 7 / 2 (0111 / 0010) demands 5 steps. I don't quite get why ...
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Why doesn't MIPS allow us to use float immediate? [closed]

My teacher said that MIPS does not include instruction helping us to add a float immediate to a register because a float immediate has to be described by at least 32 bits. However, I wonder what ...
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How do I learn-by-practicing digital circuits - MIPS R2000 (or similar) processor or board? [closed]

I already do have a book which I am studying for a university course. I've searched online to buy a development kit for MIPS R2000 (or similar) and have been suggested the MIPS CI20. Don't know if or ...
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is MIPS an assembly language or machine language

I have found resources referring to MIPS as both machine language and assembly language. They are 2 different types, machine language consists of only 0s and 1s, while assembly one deploys ...
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mips single-cycle branch verilog

I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
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Flushing in pipelined architectures

How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
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how does program counter stores the instruction memory when program is loaded? [closed]

it is mentioned in the book computer organization and design by Patterson/Hennessy page 252 that: The instruction memory need only provide read access because the datapath does not write ...
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In which CPUs will write-after-write and write-after-read dependencies cause a hazard?

I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies ...
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I-type register format maximum size of a constant

The above picture is an I-type format register. I am confused as to why the largest constant possible is $$2^{15}$$ Should the largest possible constant be $$2^{16} -1$$
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Clarification on MIPS sw and lw

If I have the following code in C A[1] = 2; Where the starting address A[0] is $s0. ...
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Clarification on R, I, and J type Instruction formats in MIPS

I would like some clarification on some concepts of register types, to know if I understand it correctly. If I had a 32-bit CPU. Would that mean that the max number of operations that can be ...
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what is the concept behind writing the testbench in the following image?

i am trying to implement an MIPS processor in Vivado ysing Vhdl.i have already written code for processor that has register file ,memory and all other functional units. Now I am trying to create a ...
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134 views

How exactly do clock speeds of computers relate to operation speeds?

I was wondering about this the other day when I was explaining binary and hexadecimal to a friend of mine and this came up. The question goes something like this: How exactly do instruction ...
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Finding percentage accuracy of instruction pipeline branch predictor

I need help in understanding the solution from solution manual. The question is from the exercise 4.24.4 and 4.24.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey ...
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235 views

Understanding execution of sequence of pipeline instructions

I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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115 views

Understanding instruction branching

I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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219 views

Understanding instruction pipelining speedup calculation

I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition): Percentage occurrences of the instructions are as ...
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224 views

Understanding processor instruction pipeline problem solution

I need help in understanding the solution from solution manual. The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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71 views

How instructions get executed in a pipelined architecture?

I saw this HW solution in CMU Comp Arch course website. I am reading ComputerArchitecture on my own. I just have a doubt. Here is the HW question: Given the following code (MIPS): ...
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997 views

5 cycle instruction forwarding - MIPS

Consider the following MIPS instructions: lw r6, 0(r1) lw r5, 0(r2) add r5, r5, r6 Assume I have full forwarding capabilities. I know that when I produce a value,...
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Why don’t most RISC ISAs write integer MULH/MUL or DIV/REM to two general-purpose registers? [closed]

Most hardware multiplication and division algorithms can compute the high and low words of a product of two integers, or both the quotient and remainder of the division of two integers, at the same ...
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436 views

Implement BGEZAL instruction-MIPS-32 in verilog

I want to implement MIPS-32 Single cycle microarchitecture using Verilog. I have few doubts regarding the instruction BGEZAL. It does GPR[31] = PC + 8. The BGEZAL ...
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what exactly is single cycle instruction architectures?

I got the following text from lab work 2 of CMU's computer architecture course. I am actually trying to do this lab myself out of own interests and I am in no way a student of CMU. The machine has ...
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Difference between MIPS and ARM datapaths [closed]

I have just learnt simplified five stage pipelined MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. ...
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immediates for MIPS I-type instructions

In MIPS, an I type instruction has the following format. bits [31, 26] are for opcode bits [25, 21] are for source register bits [20, 16] are for transfer register bits [15, 0] are for immediates If ...
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Are there any cases where single-cycle is better than pipelining?

I've been asked by my professor When pipelining is better than single-cyle MIPS CPU's? I actually answered "always", but I'm not sure that's the correct answer. Excluding an increase in design ...
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Interesting MIPS correction

I was writing a Quicksort algorithm on the Mars emulator for MIPS and I defined my array to have a particular amount of numbers. I defined the array to have six numbers and I gave the array six ...
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Why MIPS uses R0 as “zero” when you could just XOR two registers to produce 0?

I think that I am looking for an answer to a trivia question. I am trying to understand why the MIPS architecture uses an explicit "zero" value in a register when you can achieve the same thing by ...
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Analysis of Branch misprediction in MIPS 32 bit architecture

I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below. I am considering the case where there is already a branch delay slot ...
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Single Cycle Datapath MIPS - Adding swap instruction

Let's say I want to make a new MIPS instruction called: swap $rs $rt , which exchanges the contents of the registers $rs and $rt. Using an auxiliary variable aux, this new instruction is specified as ...
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Why is register file latency, during write-back stage, not included in computing for minimum clock cycle time

I was looking at the solution for a homework posted here: https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf and noticed that for 1.1, it didn't include the Register ...
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Replace ALU With Lookup Table? [closed]

Disclaimer: So this is obviously a silly question and I want to start by saying I don't want to discuss the financial costs of this, as I'm aware CPU cache is expensive. As this hasn't been made ...