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Questions tagged [mips]

MIPS is a reduced instruction set computer (RISC) architecture that has both 32 and 64-bit variants. The technology is often licensed as IP cores to manufacturers. The Microchip PIC32 series is an example of a common microcontroller based on the MIPS M4K core and several FPGAs include a MIPS microprocessor.

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Which address bit width should I choose for my single cycle CPU (Logisim)

I am currently designing a MIPS single cycle CPU (32 bits) in Logisim I have already implemented the PC, instruction memory, register file and ALU. Since it is a 32 bits system I understand that the ...
Luigi_S_R's user avatar
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Why Does MIPS IF.Flush Signal come out of the control unit?

I was reading about MIPS pipelining, specifically, the part on dealing with branching through predictions by assuming a branch is not taken, then adding nops if the ...
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Why forward from MEM Stage in a sequence of add instructions that all contain the same register?

I was reading Computer Architecture and Organization 5th edition by Patterson and Hennessy. In Chapter 4, section 4.7 on Data Hazards, I read the following excerpt regarding forwarding from the MEM ...
Juan De Castro's user avatar
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Some questions on this reduced MIPS architecture

Consider the attached discussion of a reduced MIPS microprocessor from Weste and Harris's CMOS VLSI Design. My recollection of my computer organization course is relatively weak, so I'm hoping someone ...
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Why use bytes instead of words for offsets in 'lw' and 'sw' instructions?

In assembly language, there are instructions like 'lw' (load word) and 'lb' (load byte). Both of these instructions involve adding an offset to a base address. It seems counterintuitive, however, that ...
Emad Kheyroddin's user avatar
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Alu Control output not return 010 for Addi instruction

I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
Phronesis's user avatar
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Seeking clarification on equation used in MIPS assembly problem

I'm currently studying MIPS assembly code, and I'm having trouble understanding the solution for question (b) of a particular problem. I was hoping someone could help me clarify a specific part of the ...
Frank's user avatar
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Why do we need stalls even if branches can be determined?

I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
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Help with Register File Implementation on Logisim

I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
mrAnonymous's user avatar
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Help needed with solving MIPS jump instruction encoding question

I am currently working on a project that involves understanding the encoding of MIPS assembly instructions and I am struggling with a question that I hope someone here can help me with. The question ...
Bryan C's user avatar
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How to solve pipeline hazards using stalls?

So, I have the following code, which should run on a five-stage pipeline (Fetch, Decode, Execute, Memory, Write). Now, we need only to consider read-after-write data dependencies and find the total ...
Vedanta Mohapatra's user avatar
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?

As I understand it, leakage power depends after implementation and not on the architectural level itself. When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
Nagendra Prasad's user avatar
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How is sll implemented in MIPS?

I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
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What pitch is 14-pin header adapter

the device PCB have serial console port header and 14-pins test points right next it. It marked as J303, J304. The device processor is MIPs based, so I assume that could be a 14-pins MIPS JTAG header. ...
fxgreen's user avatar
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Store byte instruction in RISC-V assembly

I have a short snippet of RISC-V assembly that I'm having trouble understanding. I'm not sure if I'm interpreting the instructions wrong, from my interpretation it seems as if the branch (BNE) will be ...
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How can I fix delay between Instruction and Program Counter?

I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing. I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
Anshul Gupta's user avatar
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C code to MIPS (offset)

Suppose $t0 stores the base address of word array, $s0 is associated with position, and $s1 is associated with offset.I have to convert the following program segment into Assembly and write down the ...
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Doubt in pipelining forwarding in MIPS

I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google I have a doubt in part ...
nmnsharma007's user avatar
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How can I modify single-cycle MIPS processor to implement jal command?

Hello Stack exchange community I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command? My most pressing confusion ...
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Single-cycle MIPS processor in Verilog (multiplexor)

I only recently started to understand in Verilog. But I have a task to create single-cycle 32bit MIPS processor. Instructions I want to implement are add, and, addi, addu.qb, addu_s.qb, beq, jal, jr, ...
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Why is there no NOR with immediate value in MIPS? AKA NORI

One thing which got me thinking was the lack of NORI in MIPS. Is the argument similar to why there is no SUB for immediate values since it can be simulated with a different instruction? If so, how is ...
Ken Gondor's user avatar
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Adding a new instruction to a MIPS

heyy, I study software so i'm absolutely new when it comes to drawing electrical circuits and I need to add a new instruction to This MIPS machine here The new instruction i have to add jt - jump ...
Lynn's user avatar
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MIPS clock cycle calculation formula

How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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Devices storing volatile memory

I've hit a bit of a rut in a question on my homework for my computer architecture class (MIPS architecture): what are digital logic devices that can implement 1 bit and 32 bit volatile memory, and ...
Muffinlicious's user avatar
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Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
RajS's user avatar
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How is the lh (load halfword) instruction implemented in MIPS?

I am a bit confused about lh (load halfword) instruction. Would it be correct to say that it gets the contents of the address just like in load word instruction but then takes the 16 rightmost bits ...
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Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
Vipin Baswan's user avatar
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MIPS Help (Modulo or Something Similar)

I have this project in MIPS and I read in user input of 10 integers into an array of length 10. After reading them I need to iterate through the array and add the odd numbers (not odd numbered ...
JackLalane1's user avatar
2 votes
1 answer
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The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
Will's user avatar
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MIPS invert - why are the 2 operands always inverted first thing?

I'm learning about MIPS 32 bit. I understand that CMOS technology uses NAND and NOR for the AND and OR commands, but still, I don't understand why is the inverter at the begining. Another thing is ...
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Verilog Reg File: Cant mix blocking and non-blocking assigment

I want to implement a blocking read to read the data as soon as it is written. I am trying to implement a MIPS 1 pipeline and i need the data to be available in the same clock it is written. The flips ...
Cholax's user avatar
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Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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How many stall cycles resulted by incorrectly predicted branch in instruction pipelining

I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy: The importance of having a good branch predictor depends on how often conditional branches ...
RajS's user avatar
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Why does 1-bit predictor miss on first iteration of inner loop next time around?

My computer organization and architecture claims that with 1-bit predictor, there are 2 mispredicts. The first miss is when mistaken on last iteration of inner loop. The second one is as not taken ...
Tki Lio's user avatar
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Overflow detection and efficiency

I know the add instruction in mips32 will do overflow detection, i.e. add $t0, $s0, $s1; I want to know whether this feature ...
Kindred's user avatar
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Why does a divider needs 1 more step?

My book introduces a divider design: It said that if the divisor is n-length number, we need n+1 steps to finish the division. For example: 7 / 2 (0111 / 0010) demands 5 steps. I don't quite get why ...
Thong Nguyen Thanh's user avatar
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Why doesn't MIPS allow us to use float immediate? [closed]

My teacher said that MIPS does not include instruction helping us to add a float immediate to a register because a float immediate has to be described by at least 32 bits. However, I wonder what ...
Tki Lio's user avatar
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1 answer
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How do I learn-by-practicing digital circuits - MIPS R2000 (or similar) processor or board? [closed]

I already do have a book which I am studying for a university course. I've searched online to buy a development kit for MIPS R2000 (or similar) and have been suggested the MIPS CI20. Don't know if or ...
firstName lastName's user avatar
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4 answers
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is MIPS an assembly language or machine language

I have found resources referring to MIPS as both machine language and assembly language. They are 2 different types, machine language consists of only 0s and 1s, while assembly one deploys ...
Tjh Thon's user avatar
1 vote
2 answers
3k views

mips single-cycle branch verilog

I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
Ctuohey's user avatar
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1 answer
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Flushing in pipelined architectures

How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
Rajat's user avatar
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how does program counter stores the instruction memory when program is loaded? [closed]

it is mentioned in the book computer organization and design by Patterson/Hennessy page 252 that: The instruction memory need only provide read access because the datapath does not write ...
Fatemeh Karimi's user avatar
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1 answer
593 views

In which CPUs will write-after-write and write-after-read dependencies cause a hazard?

I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies ...
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I-type register format maximum size of a constant

The above picture is an I-type format register. I am confused as to why the largest constant possible is $$2^{15}$$ Should the largest possible constant be $$2^{16} -1$$
user3067059's user avatar
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Clarification on MIPS sw and lw

If I have the following code in C A[1] = 2; Where the starting address A[0] is $s0. ...
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Clarification on R, I, and J type Instruction formats in MIPS

I would like some clarification on some concepts of register types, to know if I understand it correctly. If I had a 32-bit CPU. Would that mean that the max number of operations that can be ...
user3067059's user avatar
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what is the concept behind writing the testbench in the following image?

i am trying to implement an MIPS processor in Vivado ysing Vhdl.i have already written code for processor that has register file ,memory and all other functional units. Now I am trying to create a ...
Aditya Tumsare's user avatar
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How exactly do clock speeds of computers relate to operation speeds?

I was wondering about this the other day when I was explaining binary and hexadecimal to a friend of mine and this came up. The question goes something like this: How exactly do instruction ...
user108391's user avatar