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ocrdu
ocrdu
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SPI vs Parallelparallel data/address bus - speed and data troughput

I have a digital board (developed more than 10 yearyears ago) which has a DSP and aan FPGA, that communicate over a parallel 16-bit data + 16-bit address interfaceparallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP. 

I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to a SPI interfacemove to an SPI interface for the communication between the two ICs, in order to reduce the amount of used pins (fromused from at least 32 pins + control signals) to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing tothe use if a smaller package for the DSP, and also lessfewer PCB layers.

I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what are the design constraints I should evaluate are, at a first glance. 

Moreover, I would like to know:

  • whatWhat is usually feasible as maximum SPI speed (overfor components on the same PCB);
  • what isWhat the preferred solution is, today, for communication between logic ICs on the same board;
  • if SPI blocks for communication are usually available as IP blocks from FPGA vendors.

Thanks, Alessio

SPI vs Parallel data/address bus - speed and data troughput

I have a digital board (developed more than 10 year ago) which has a DSP and a FPGA, that communicate over a parallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP. I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to a SPI interface for the communication between the two ICs, in order to reduce the amount of used pins (from at least 32 pins + control signals) to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing to use a smaller package for the DSP and also less PCB layers.

I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what are the design constraints I should evaluate, at a first glance. Moreover, I would like to know:

  • what is usually feasible as maximum SPI speed (over components on the same PCB);
  • what is the preferred solution, today, for communication between logic ICs on the same board;
  • if SPI blocks for communication are usually available as IP blocks from FPGA vendors.

Thanks, Alessio

SPI vs parallel data/address bus - speed and data troughput

I have a digital board (developed more than 10 years ago) which has a DSP and an FPGA that communicate over a parallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP. 

I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to an SPI interface for the communication between the two ICs, in order to reduce the amount of pins used from at least 32 pins + control signals to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing the use if a smaller package for the DSP, and also fewer PCB layers.

I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what the design constraints I should evaluate are, at a first glance. 

Moreover, I would like to know:

  • What is usually feasible as maximum SPI speed (for components on the same PCB);
  • What the preferred solution is, today, for communication between logic ICs on the same board;
  • if SPI blocks for communication are usually available as IP blocks from FPGA vendors.
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Alessio Caligiuri
Alessio Caligiuri
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SPI vs Parallel data/address bus - speed and data troughput

I have a digital board (developed more than 10 year ago) which has a DSP and a FPGA, that communicate over a parallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP. I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to a SPI interface for the communication between the two ICs, in order to reduce the amount of used pins (from at least 32 pins + control signals) to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing to use a smaller package for the DSP and also less PCB layers.

I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what are the design constraints I should evaluate, at a first glance. Moreover, I would like to know:

  • what is usually feasible as maximum SPI speed (over components on the same PCB);
  • what is the preferred solution, today, for communication between logic ICs on the same board;
  • if SPI blocks for communication are usually available as IP blocks from FPGA vendors.

Thanks, Alessio