I have a digital board (developed more than 10 years ago) which has a DSP and an FPGA that communicate over a parallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP.

I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to an SPI interface for the communication between the two ICs, in order to reduce the amount of pins used from at least 32 pins + control signals to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing the use if a smaller package for the DSP, and also fewer PCB layers.

I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what the design constraints I should evaluate are, at a first glance.

Moreover, I would like to know:

  • What is usually feasible as maximum SPI speed (for components on the same PCB);
  • What the preferred solution is, today, for communication between logic ICs on the same board;
  • if SPI blocks for communication are usually available as IP blocks from FPGA vendors.
  • \$\begingroup\$ SPI speeds depend on the "receiver" as does I²C, a MCP4921 can do 20MHz, both SPI & I²C are great, You can use analog switches, like CD4051 or similar / dedicated I²C switches to relay the signals between "devices" to over come addressing problems. \$\endgroup\$ Feb 9, 2023 at 16:02
  • 1
    \$\begingroup\$ What's the data transfer rate? \$\endgroup\$
    – user253751
    Feb 9, 2023 at 17:05
  • 1
    \$\begingroup\$ What clock did the old bus run at? \$\endgroup\$
    – datenheim
    Feb 9, 2023 at 21:45
  • \$\begingroup\$ Old bus is at DSP's clock: 150MHz \$\endgroup\$ Feb 10, 2023 at 11:14

3 Answers 3


SPI is conceptually quite simple. This bus was originally designed to be used with a simple shift register in target devices. The basic protocol is flexible and customizable. Some simple SPI devices have literally just a chain of flip flops in the device. The clock shifts in the data on MOSI into the chain, and out MISO. Chip select enables the whole chain. This sort of thing is common with RF digital step attenuators.

Speed: If the DSP has an embedded peripheral SPI master, then you can probably run at 25-100 MHz clock rate. If not, then you will be bit-banging, and the speed will be limited and the DSP core will have to toggle the pins as needed. In this case, you are probably looking at somewhere around 1 MHz SPI clock rate, plus a hit to the DSP core since it will be toggling pins while communicating instead of being free to do DSP things.

The harder part is adapting the protocol in a way that makes sense for your application. The length of SPI transactions are up to the application. In this case, you need 16 address (I think), and 16 data clocks for writes. For reads, you have to consider if you need wait states after the address phase.

SPI's simplicity comes with some compromises:

  1. There is no native way to pause a transaction by the slave (target).
  2. There is no built in error checking (in contrast to I2C).

Most FPGA vendors do have some sort of SPI logic IP you can use (often this is free). Personally, I have found it is easier to just craft what you want with behavioral code instead of having to work around their defined interfaces.


SPI is still popular as a medium speed chip to chip link, as a faster option to UART or I2C. It’s especially popular for NOR flash but also sees use for peripherals like DACs and ADCs, and for linking processors.

(TI has their DSP serial chip-to-chip standard called McBSP, which is SPI-like. Very old. More here: https://www.ti.com/lit/ug/spru061d/spru061d.pdf)

Basic SPI clock rate is largely limited by the total turn-around time for read data, along with the usual strategy of using opposite clock edges for drive vs. sampling. Both SPI characteristics, and the fact that it uses ordinary logic I/O, eat into read data setup time at the controller. As a consequence, typical SPI clock speeds are limited to 50MHz or so.

You can mitigate this issue if you create a separate receive clock with additional delay to capture the read data. Some microcontroller SPI implementations do this, notably NXP and ST. With careful design this gets you 100MHz or so.

SPI also supports wider operation: 2, 4 or even 8 bits. (4 is a popular option with SPI flash.) Using QSPI can get you 25-33MB/s (50-66MHz clock.)

As for IP, you're in luck. SPI is popular enough that FPGA vendors include it as standard. Xilinx has QSPI as a base library block in Vivado. It supports AXI4 and AXI4-Lite host interface. More here: https://www.xilinx.com/products/intellectual-property/axi_quadspi.html

Beyond this, there’s Xccela and Hyperbus which are 8-bit extensions of SPI (octo-SPI.) Hyperbus and Xccela are a lower pin-count alternative to separate DDR and Flash interfaces. They support source-synchronous DDR clocking, so can achieve up to 400MB/s throughout with a 200MHz DDR max clock. CAST and others offer this as an IP block. More here: https://www.cast-inc.com/peripherals/memory-controllers/xspi-mc

Another thing to consider: Xilinx Aurora which can be used to serialize AXI or other parallel protocols. You'd need an Aurora serdes solution for your DSP of course (perhaps a low-end Artix.) More here: https://docs.xilinx.com/r/en-US/pg074-aurora-64b66b

Yet another option is RMII or RGMII via an Ethernet switch or perhaps point-to-point.


In this table you will find all you need to know about communication protocols.

  • 1
    \$\begingroup\$ I don't think UART is a popular interface for inter-IC communication especially if the IC serves a specific purpose. Furthermore, UART can be full-duplex with two wires and definitely can go above 0.2Mbps rates. \$\endgroup\$
    – Mu3
    Feb 10, 2023 at 13:13

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