I have a digital board (developed more than 10 years ago) which has a DSP and an FPGA that communicate over a parallel 16-bit data + 16-bit address interface. In the FPGA, there is a sort of dual-port RAM to exchange data with the DSP.
I am redesigning this board and, from an architectural point of view, I am evaluating if it is worth to move to an SPI interface for the communication between the two ICs, in order to reduce the amount of pins used from at least 32 pins + control signals to only 4 signals (SPI SIMO & MOSI + CLK + CS), allowing the use if a smaller package for the DSP, and also fewer PCB layers.
I know that it is difficult to give a response without any specific data on the application. In fact, at this stage of development, I would like to know what the design constraints I should evaluate are, at a first glance.
Moreover, I would like to know:
- What is usually feasible as maximum SPI speed (for components on the same PCB);
- What the preferred solution is, today, for communication between logic ICs on the same board;
- if SPI blocks for communication are usually available as IP blocks from FPGA vendors.