Why does MOSFET N back to back switch work?

Question

Please consider an exemplary back-to-back MOSFET N driver IC (drew the body diodes of M1 and M2 for clarity):

I understand how is it possible to turn off the M1/M2 transistors from the gate voltage point of view (since its higher than VIN voltage due to the internal charge pump). What I do not grasp is why do the transistors turn on when the gate voltage goes high and VIN voltage appears, since the sources of the transistors are "floating". The sources potential is not fixed to voltage value (lower than the gate voltage) before the M1 starts conducting. Question is, why does it start conducting in the first place? How to understand this phenomena?

Answer 1

FETs have a neat party trick: they can conduct in both directions. And, a bias on gate-to-drain will turn on the FET as well as the more customary gate-to-source.

In this circuit then, the left-hand FET will be on, bringing up the source for both: the two sources will be at the same voltage as the left-hand FET drain. So the right hand FET will also be on.

This slide deck gives more information about how FET biasing works. tl, dr: it’s about gate to substrate bias. https://alan.ece.gatech.edu/ECE3040/Lectures/Lecture24-MOS%20Transistors.pdf

One detail: the IC brings the gate voltage above both FET drain and source voltages since n-FETs are being used. This ensures that turn-on will occur, since Vgs is higher than threshold.

Answer 2

If you read the datasheet, the IC has a charge pump that produces 13.1V above Vout and the common source node never floats more than M2's body diode drop above Vout.

Answer 3

A reverse diode still conducts, with \$I = I_s(e^{V/V_f}-1)\$. At significantly reverse bias, the current is the saturation (leakage) current. At no time is the common node floating, it is just high impedance.

Answer 4

Because the FET has a reverse diode from S to D, the S of the 'other' FET cannot be more than 0.7 V above that drain. So, the common S node is no higher than the lowest of either drain. Therefore if GATE is lower than both drains, then both FETs will be off.

Consider M2. and a load at 10 V. Therefore SS can't be higher than ~ 10.7 V. now if the GATE is at 0V, M2 will be OFF, and S can remain no higher than 10.7 V. If VBATT is higher than 0 V, M1 will also be off and will provide the desired blocking.

Note that node SS can now be at any votlage between ~ 10.7 V and 0 V -- it is floating in that range. but no matter what value it is at, M1 will be off, so no curent can flow. M2 will be off also.

This is not acomplete circuit. FETs need their VGS held to less than 10 V (usually), and you cannot have VG-D more than that either (you can have VD-G mucch higher). Thus you usually have a zener ciruit to limit VGATE to no more than 10 V above the lowest of drain1, drain2, and no more than 10 V below the lowest V either.