How a 2-1 multiplexer (MUX) work?

Question

I haven't done EE for quite a long time. I need to implement some MUX, so I started with a two-way MUX. But I don't understand how to make the decision:

Wiki- Multiplexer

A truth table will show that

This truth table shows that when S=0 then Z=A but when S=1 then Z=B.

I don't get the logic here. The boolean expression is Z = (A and S') or (B and S)

---

Let S = 0, then each sub expression will become

　　　　　　　　　　　　　　　　z1

A = 0,　　S'　= 1　　　=> 0

A = 1,　　S'　= 1　　　=>　　1

　　　　　　　　　　　　　　　　z2

B = 0,　　S =　0 　　　=>　0

B = 1,　　S =　0 　　　=>　0

Can someone please explain to me how do we reach that conclusion? Thank you very much!

Answer 1

The best way to get a proper understanding is to write down the truth table completely. You have 3 inputs (A, B, S), so this will give you 2\$^3\$ = 8 combinations:

S  A  B | S' C  D | Z
--------+---------+--
0  0  0 | 1  0  0 | 0
0  0  1 | 1  0  0 | 0
0  1  0 | 1  1  0 | 1
0  1  1 | 1  1  0 | 1
1  0  0 | 0  0  0 | 0
1  0  1 | 0  0  1 | 1
1  1  0 | 0  0  0 | 0
1  1  1 | 0  0  1 | 1

It's often useful to add intermediate results to make things more clear. I added a term \$C = (A \land S')\$ and \$D = (B \land S)\$. Now it should be clear that \$Z = (C \lor D)\$.

Answer 2

One point not yet mentioned is that in many cases, the proper expression is Z = (A and S') or (B and S) or (A and B). The last term is used if A and B are both set and S changes from zero to 1 or vice versa. In that scenario, without the last term, the output might go low briefly. Adding the last term will ensure that when A and B are both set, the output will remain set. This has at least two useful effects: (1) it will prevent problems if the Mux is used as part of the sequencing logic in a circuit. For example, a Mux whose output is tied to an input makes a nice latch, but only if the output doesn't glitch when S changes; (2) in CMOS logic, such a design may reduce energy consumption when S changes, since the momentary glitch resulting from a change in S might cause shoot-through currents.

Answer 3

Let S = 0, then each sub expression will become

　　　　　　　　　　　　　　　　z1

A = 0,　　S'　= 1　　　=> 0

A = 1,　　S'　= 1　　　=>　　1

　　　　　　　　　　　　　　　　z2

B = 0,　　S =　0 　　　=>　0

B = 1,　　S =　0 　　　=>　0

So, This means that When S=0, Irrespective of Input B, Output will depend only on Input A. If you make S=1, MUX will select Input B. Which means Output will reflect only B. It will not have any effect of A.

Let's take Main Boolean Expression:- Z = (A and S') or (B and S)

When S = 0;

Z = (A and 1) | (B and 0)

Z = A | 0

Hence Z = A

When S = 1;

Z = (A and 0) | (B and 1)

Z = 0 | B

Hence Z = B;

Answer 4

In this simple case you can (almost?) design the circuit in English.

Depending on S, you want either A or B to appear on Z. So you want a 1 on Z when ( A is selected and A is one), or when ( B is selected and B is one ). In all other cases the selected input is 0, so you want a zero on the output.

Distilling the expression: ( A is one and A is selected ) or ( B is one and B is selected ) A is selected means: ( S == 0 ) B is selected means: ( S == 1 )

make it more formal: ( A ^ ~ S ) V ( B ^ S )

so you need an OR, tow ANDs and one inverter.

Answer 5

A MUX is simply a logic switch of sorts. The S_0 signal (select signal) will pass the A signal if it is low (logic 0 or 0v) and pass the B signal if it is high (logic 1 or +5v or whatever voltage the system uses).

The same can be applied to a 4 to 1 MUX. The select signal acts as a binary number selecting which incoming signal's truth value is passed through. If you think of the MUX as vertical like this:

     ________
    |4to1MUX |
    |y0      |
    |y1      |
    |y2     F|
    |y3      |
    |        |
    |_s1__s0_|

The input signals are laid out from least significant to most significant and the select inputs are laid out most significant to least significant. When a "00" is applied to the select lines then y0 is selected. When "01" is applied, y1 is selected; "10",y2; "11",y3.

The other post are very helpful in explaining the Boolean algebra parts, which are found by examining the truth table as said elsewhere.