Using Logic-Analyzer to reverse-engineer ISM-band ASK/OOK encoding, possible?

Question

Is it possible to use a Logic Analyzer (such as this one), to determine the waveform s.t. on the DATA out pin of an ISM-band ASK/OOK (315/433.92MHz) RF module, in turn to decode it's encoding scheme. I know for sure that it is not Manchester/NRZ. By 'waveform', I mean the highs/lows with the duration of every bit

Note that this questions is an extension of my other thread on choosing a DSO. While I might still go in for a DSO, but I really wanted to thoroughly understand the LA as an option for my purpose.

Now for the other (possibly dumb) question -- will a logic-analyzer work without a clock input ? Say in my case of decoding ASK/OOK encoded data, I have no way to retrieve the clock, as this is asynchronous operation.

Query extension (Nov 9, 2011): My target RF encoder's encoded pattern uses 32 oscillation cycles to encode every bit. So for 9600baud, I have 307200 sample/sec. However, for better accuracy, it might be good to use 3x-5x that many no. of samples (does this concept apply for Logic Analyzers as well) ? If that is true, then for 5x sampling, I'd need 1536000 (~1.5Ms/s), on a single channel. Of course, this reasoning for (kind-of over-)sampling comes from the DSO world, but not sure if it applies for Logic-Analyzers as well ?

Answer 1

I did exactly that in a previous project, I didn't use the open logic analyzer but the bus pirate which uses the same software.

http://s3cu14r.wordpress.com/2011/06/19/basic-rf-sniffing-with-the-bus-pirate/

I used this to decode the protocol for another project that sniffed RKE data.

http://hackaday.com/2009/10/03/garage-door-packet-sniffer/

Hope this helps.

Answer 2

To answer the added part of your question:

Yes, the sampling rate applies to logic analysers too. Obviously the signal state will be accurately represented as it can only be 0 or 1 (unlike a DSO), but the higher the sampling rate the more accurate the timing.
For instance if you have the following:
Data:
__---_-____---____---_-____---____
LA Sample clock:
--__--__--__--__--__--__--__--__--
LA Display:
____----____----____----____----__

If we assume the logic analyser samples on the rising edge of the clock, you can see how it can get the timing slightly out or miss a change altogether.
You will never miss a change providing the sample rate is at least twice the data rate, but the actual timing of the changes will be less and less accurate as you approach this point.
In your case, the LA you link to will easily cope with a 300kHz toggle rate, as it's sampling at up to 200Msps, which will give you accuracy to +/- 5ns. Since the data only changes every 3.3us or so, the logic analyser will be very accurate as it can sample 666 times during this period.

Answer 3

The sampling rate used for digital signals depends on the data rate as well as duty cycle, for example, let's say you have a 1khz data signal with 50% duty cycle, sampling at 2khz or over will give reliable results since you only need to check on both sides of the transition.

Now if you have a 1khz data signal with a 10% duty cycle you need to sample at at least 10khz to ensure you get every part of the waveform. With digital signals like these the sampling rate hardly matters since you'll probably just have it set up with an interrupt anyway. The only place it is important is when using a logic analyzer and in this case you can just use auto or try it a couple of times.