ADC with I2C interface with multiple addresses

Question

I want to connect 31 ADC slaves to a master. The ADCs simply should measure voltage and response its values to the master after request. I thought about using I2C as bus system. The problem is that most ADC ICs with I2C interface only offer 2 or 3 bits for address (4 or 8 addresses possible) I need 5 bits for my 31 addresses. What can I do to use 31 I2C ADC slaves in one bus system? Are there such devices like address mappers, expanders, switches, multiplexers? What is common and good practice for my requirements? The reason I would like to use a bus system is to keep wiring and pin usage of the master low.

To be more specific I need to measure voltage from multiple in series connected sources:

^{simulate this circuit – Schematic created using CircuitLab}

I am aware of that I need to provide a galvanic isolation between I2C master and slaves. I am afraid that I cannot use multichannel ADCs in this case am I right?

Answer 1

You didn't specify the A/D speed or accuracy, so any A/D will do.

One possibility is to use A/D chips with multiple input channels. You can find them with 8 or 16 or even more inputs. These are essentially a A/D with a analog mux front end integrated into a single package. Four 8x A/Ds would do it, and you can probably find some that do IIC and have at least 2 address bits that can be set via the pins.

Another possibility is to use a small micro with a large number of A/D channels. This is like the previous case in that there is a analog mux integrated with the A/D, but there is also a microcontroller integrated with it. The integrated micro can then do the continuous sampling, perhaps some low pass filtering, and communication back to the master. Now you're not limited to IIC, although many micros have IIC hardware that can act as a slave device. Since the address is set by firmware, you can have as many of these on a IIC bus as it can electrically handle. However, no more than 2 would be needed since a number of micros have 16 or more A/D channels.

Answer 2

There are quite a few SPI bus ADCs that can be daisy chained together. This means they all receive a common clock and "start conversion" signal but the data output from the "furthest" ADC feeds the data input of the next furthest. They all convert simultaneously and the last in the ADC chain clocks out all 31 slave values: -

Master MISO in the above diagram only connects to the lowest slave's data. It in turn receives data from the middle slave as its own data is being clocked out.

Here's another diagram: -

Answer 3

A better way to handle your requirements would be an IC like Linear's LTC 6803-2/4 series. They can hadle up to 12 cells per IC, and moreover the ICs can be stacked together with isolation. You need to interface them with a micro using SPI though.