I'm not sure if I missed something, or it's omitted from the datasheet, but in any case, I couldn't tell what happens on the output when the selected input is floating. This post seems to imply there is a defined value for (most?) multiplexers.
I'm trying to implement this schema for the reasons in the question, and I'm not sure I would be able to use a digital multiplexer like CD54HCT151.
(Ignoring the effects of any enable controls on multiplexers...)
An analogue multiplexer makes a low impedance connection between its output and the selected analogue input. This is to pass the selected analogue voltage waveform straight through as best it can.
A digital multiplexer drives its output to the same digital level as that on the selected digital input. This will probably be implemented by an AND-OR tree internally.
The digital input resolves the voltage to a logic high or low, like the input of any other logic gate (74HCT here). Although some logic families have a linear region, it is minimal on 74HCT. Therefore the output voltage will be resolved, by and large, as well as an 74HCT inverter or any other 74HCT gate would.
The data sheet does cover this. It specifies the input voltages and currents that must be met for true logic levels to be detected. It is the responsibility of your driving circuit to make sure that it presents these voltages to the logic inputs. It also specifies the resultant output voltages and currents that the gate will produce when signalling a logic high and logic low.
With CMOS logic parts such as this, any unconnected input may float to any value - High, Low or indeterminant, as the inputs are very high impedance.
ALL inputs to CMOS logic parts MUST be connected to something: the output of another CMOS part, or pulled high or low via a resistor to Vcc or Ground, or tied directly to Vcc or Ground.
