How does this two op-amp relaxation oscillator function?

Question

How does the following circuit with two TL082 op-amps function?

Where should we start thinking about the logic of this oscillator circuit? I named the nodes in red as A, B, C and D.

1. How can we explain the output oscillation in terms of voltages at the nodes step by step? In a manner like: "Voltage builds up at D then this happens, and so forth and so on..."

2. In my simulation I don't get +-5 V pulse output, I get around +-3.5 V output and the output starts oscillating very late, why? Here is what I get:

BTW, does this circuit have a specific name in literature? It is an oscillator with negative feedback, but other relaxation oscillator examples I have seen have positive feedback.

Answer 1

Firstly, the TL082's output will only typically swing to + & - 1.5 V from the supply rails and so with a + & - 5 V supply, the output will saturate at about + & - 3.5 V. This is the reason for your limited output swing.

Let's assume that Vout has just switched to + 3.5 V. Point D will be at +1.75 V. Point C has been forced to rise instantly to 3.5 V as has point B. Because the inverting input of the comparator on the left has its inverting input at a higher voltage than its non-inverting input, point A will be at -3.5 V and because the comparator on the right has its inverting input at a lower voltage than its non-inverting input, the comparator on the right is forced to drive its output to positive saturation (+ 3.5 V) as we initially assumed.

All seems well except that this situation is not stable. Because point C is at +3.5 V and point A is at -3.5 V, the capacitor will start to charge and the voltage at point C will start to fall exponentially. When the voltage at point C reaches 0 V, the left hand comparator's output (point A) will switch to +3.5 V, the right hand comparator's output will switch to -3.5 V taking point D to -1.75 V and points C & B instantly down to -3.5 V.

Again we have an unstable situation with point C at -3.5 V and point A at + 3.5 V forcing the capacitor to start charging exponentially. When the voltage at points B & C has risen far enough to reach 0 V, both comparators switch states and we are back where we started with point D at +1.75 V, points and B & C at +3.5 V and point A at -3.5 V. Now, as before, the voltage at point C falls exponentially and the sequence repeats....

Answer 2

1st: recognize these Op Amps and that the 1st is used as a unity DC gain with differentiator feedback on the output of the 2nd stage.
The 2nd stage is used as a comparator looped back with positive feedback, but if has 0 input the output is 0.

2nd: recognise current limit of Op Amps and too low feedback R like 220 ohm may cause current limits. This design could easily be scaled by increasing all R's x 100 and reduce C by the same ratio /100 to get the same RC=T.

3rd: if the initial condition does not start a ramp voltage on the cap, it has nothing to differentiate.

Step 1: Assume all inputs and outputs are at 0V with Vcc,Vee=+5,-5V.
U1 is scaled to 50% and so the R divider output (D) has an output of +/-2.5V with a source Req=1.1k

Step 2: Since the in+ ref= 0V the comparator output will amplify noise initially so the output of U1 may be high or low. (contrary to your simulation, which has unknown or no noise)

Step 3: If U2 is unity DC gain the output stays at 0V. what will U1 do? This looks like an integrator with high DC gain. But with negative feedback the integrator tends to correct itself and stay at zero unless there is an input offset voltage in the simulation. Perhaps this is why it took a minute to finally oscillate.

Step 4: What happens at the input of U2? When U1 out finally starts to ramp the input is attenuated at U2 by the feedback R 220 ohms with a source of Req=1.1k or about 8% of the output of U1. Since U1 has open loop gain, I am expecting the input to be microvolts and very slowing ramping with a slow but accelerating ramp.

This is getting tedius. It's a poor design with a split supply. It works best with a single supply with a split supply crossover threshold to start the ramp immediately.

The start up ramp relies on input offset voltage and a 1 minute start up ramp implies to me a 0 offset simulation.

If the Op Amps have no offset, then only simulator noise will eventually get enough picovolt error to slowly ramp. It's almost an ideal integrator until it accelerates with positive feedback to get into a realxtion mode with hystereis.

The CMOS logic Schmitt Inverter works best with a single RC as a Relaxation oscillator for a general purpose RC clock.

Answer 3

It is the same circuit as this one: