Verilog: Data Transfer using inout ports

Question

I have an EEPROM following I2C protocol. My write operation was fine. While a read operation, SDA being my inout pin, during data transfer from slave, I held the pin in high impedance (Z).I received logic zero correctly but not logic ones.Clock cycles where logic 1 was expected, were showing up high impedance state.

My question is for data transfer from slave to master, should master hold the inout pins in high impedance state? If yes then why is that when data is logic 0, cycles are showing up but when data is 1, still high impedance is observed.

Is there any other value should this inout pin be assigned to so that logic 1 and logic 0 are properly transmitted?

Answer 1

Since you are 'observing' high impedance, I take it this a simulation and not a real circuit.

In these cases, place a pullup on both sda and scl in your testbench (which presumably connects your i2c module with the eeprom model).

Answer 2

VHDL provides a solution using 9-state logic (STD_LOGIC type):

For I2C pins, and any other open-drain pins (weak pull-up), you should drive H and 0 (not Z). If any signal is simultaneously driven with H and 0, the 0 will win (as you desire) and you will not get X like you would between conflicting 0 and 1. And then use the TO_X01 function when reading the signal, to resolve H to 1.

I would look to see whether Verilog has any logic type which supports weak states.