Can a resistor mitigate a maximum input voltage limitation?

Question

I have a microcontroller running at 5v and outputting a digital signal. This signal can be high, low or high-impedance (tristated).

This signal goes to an input pin on a target chip (the type of which is not known in advance), which may be running at 3.3v or at 5v. Therefore, I need some way to limit the "high" signal to the VCC of the target.

Ordinarily, I would use a level shifter, but they don't support tristate. I could use a tristate buffer, but that's a whole extra chip - not to mention the extra control pin.

Could I use a resistor?

I may be wrong, but I believe the "maximum input voltage" limitation on chips is due to current - often current through an internal protection diode. If I used a 10K resistor, surely so little current would flow into the input as to represent no danger to the target?

It did occur to me to use a resistor AND a diode to VCC, thus limiting the voltage to VCC+0.6v.....but might this cause issues with the tristating?

EDIT: Added diagram for resistor + diode. Would this work? Or would it cause issues with the tristating?

Only problem I can think of is, in the absence of target VCC, it will be supplied a 4.4V VCC from the signal. So I would need to avoid setting the signal high when the target didn't have power applied. Am I right?

EDIT: Clarification:

I think perhaps some of you are misunderstanding the question. The output signal (at 5V, 0V or floating) has to be safe (and a valid high/low/hi-z) for all 5V and 3.3V targets, which are likely to be microcontrollers. Will my resistor-and-diode solution work? Or, will just a 10K resistor work?

Answer 1

5V logic IC's without hysteresis usually have a Vih >=0.70 Vdd which at 5V >=3.5V but at -10% = 4.5V is 3.15V.

To limit Iin(abs. max) to target 3.3V device from 5V to 5mA even though many CMOS ESD protection diodes can handle 20mA, a series resistance may be included of (5-3.3)/5mA = 340 ohms and 1K to 10K may be used with a safety margin unless rise time is a major concern with < 5pF per gate.

Thus a simple solution is to choose a 5V driver with 1k series resistance added.

^{simulate this circuit – Schematic created using CircuitLab}

Even though adding 1k appears to be redundant, it allows one to verify the action of the ESD protection on the 3.3V interface and Iih input current from measuring the voltage drop if you wish to verify using a 5V driver.

ESD dual-stage diode protection is what allows all CMOS which is universally designed to be protected with the Human Body Model, JEDEC: JESD22−A114 4kV 100pF discharge.