A typical structure of an op amp input looks like a differential pair; a simplified model of how one generally looks is shown below:
simulate this circuit – Schematic created using CircuitLab
The two transistors Q1 and Q2 are laid out carefully for optimal matching using techniques like common-centroid, interdigitation, etc - their saturation current, beta, and other relevant parameters are held as close to identical as possible.
Since an op amp is generally used in feedback and the datasheet DC characteristics often assume feedback and linear behavior, we will make the same assumption. The beauty of this structure is that it responds to differential signals, but very little to common mode ones, and because we're in feedback the differential signal is very small.
The differential pair bias current is split equally across the two branches, and is constant1 as a result of the construction of the differential pair; this means that as long as the two transistors remain in their forward-active mode, each will draw a base current of \$I_{BIAS}/2\beta\$.
It's worth noting that the input bias current isn't necessarily sunk into the chip; it may be sourced from the chip, e.g. in the case of a PNP differential pair.
Of course, as we relax the simplfications, we lose the constant behavior. Non-idealities of the tail current source (or in the worst case, a pseudodifferential pair or a common tail resistor) will lead to a varying current, and more advanced input structures can also make the current vary with common-mode voltage.
As a result, designers should generally assume that the bias current is an unknown value up to the datasheet guarantee (a worst-case value). By also assuming that the input bias is matched across both sides, it's then easy to null the effect of the input bias current by ensuring that both input pins "see" the same driving impedance. My existing answer shows an example of how this analysis and design trick can be applied to an entire op amp circuit used for gain.
1 Here, constant means that it's constant for a given chip, at a given supply voltage, at a given temperature. It will vary with manufacturing variations, supply voltage variations, and heating.