What is gpio bank?

Question

embedded and BSP newbie here. Recently I found a term named "gpio bank", but I cannot find good resources from google.

1. What's it?
2. difference of gpio bank and gpio controller?
3. difference of gpio bank and pin

linux kernel code sample:

    soc->bank_num = of_irq_count(child);
    if (soc->bank_num == 0 || soc->bank_num > GPIO_MAX_BANK_NUM) {
        dev_err(&pdev->dev, "Invalid gpio bank(irq)\n");
        return -EINVAL;
    }

    for (i = 0; i < soc->bank_num; i++) {
        res = platform_get_resource(pdev, IORESOURCE_MEM, i);
        if (res == NULL) {
            dev_err(&pdev->dev, "no mem resource for gpio[%d]!\n", i);
            return -ENXIO;
        }

        soc->regbase[i] = devm_ioremap(&pdev->dev,
                        res->start, resource_size(res));
        if (soc->regbase[i] == 0) {
            dev_err(&pdev->dev, "devm_ioremap() failed\n");
            return -ENOMEM;
        }
    }

Answer 1

GPIO = General Purpose Input Output, referring to pins that send and/or receive single bits of digital information (high/low voltage).

A GPIO 'bank' is a group of GPIO bits that can be accessed simultaneously by the CPU or DMA. The number of bits in a group is usually limited by the size of the internal data bus, so for example an 8 bit MCU with 24 I/O pins would need at least 3 GPIO 'banks'. Sometimes the bits are split into more banks because some work at different voltages or have alternate functions, or because the particular package doesn't have enough pins to bring out all the bits in a group.

A GPIO 'controller' is a circuit in the MCU that controls the operation of GPIO pins. The term is typically used in sophisticated I/O systems which may need to perform operations independently from the CPU. Simple systems often just have control registers which the CPU writes to for configuring pin direction etc.

Answer 2

GPIO pins on microcontrollers and FPGAs are often grouped together in what is sometimes referred to as a "Bank".

All the pins within a bank will have their own power supply pin/s. So one bank could be using 3.3v logic while another could use 1.8v logic, for example.

Answer 3

I've never had to use this term, so I looked it up and found many good resources.

https://docs.microsoft.com/en-us/windows-hardware/drivers/gpio/partitioning-a-gpio-controller-into-banks-of-pins

 Typically, a GPIO controller driver chooses to partition a GPIO controller into two or more banks for one of the following reasons:

   The power state of the GPIO pins in a bank can be managed independently of the pins in the other banks.
   The total number of pins in the GPIO controller is greater than 64.

https://www.realdigital.org/doc/e5be4c80924046606f8a9db3103adb91 etc

There are 4 banks; banks 0-3. Banks 0 and 1 connect to the MIO interface and goes to external pins on the chip. Banks 2 and 3 Go through the EMIO and are routed to the PL fabric  
Each bank is 32-bits wide, with the exception of Bank1 which is 22 bits wide. Each bank has the registers shown in the single channel diagram, and each bitfield of each register corresponds to a a GPIO channel. Bank 0 [31:0] maps to MIO [31:0], Bank 1 [21:0] to MIO [53:32], Bank 3 [31:0] to EMIO [31:0], and Bank 4 [31:0] to EMIO [63:32].
The registers are described below, [n] is the bank number
DATA_RO[n] Reads the input values of pins configured as inputs
DATA[n] Holds the output values of the bank.
DIRM[n] Configures which channels in the bank are outputs or inputs.    
OEN[n] Enables Channels in the bank that are configured as output to be driven.    
There are additional registers for configuring GPIO interrupts. These are covered in a seperate document.