Consider two clock signals, clk A and clk B.
Looking between two successive rising edges of clk A (the period), if we ever two or more rising edges of clk B then clk B is running faster.
If we don’t see any clk B edges then clk A is faster.
If we see exactly one clk B edge then they’re sort of close and we have to keep looking until we see a doubled or missing clk B.
In the simple circuit below we’re trying to detect two clocks in a row before the other clock has a chance to reset the first flop via an asynchronous reset.
Any time a clock arrives it sets its first flop and resets the other clock’s first flop.
If the 2nd flop ever triggers then that clock is faster and it sets or resets the final flop, latching the result for us to view with LEDs.
It is impervious to pulse width variation since it only looks at positive edges.
This algorithm could be implemented any number of ways but OP asked for 7CHC solution. Regardless of implementation, this algorithm has advantages over brute force "measure frequency or period and compare results" schemes because it directly determines "faster or slower?" without limitations of measuring period which both digital and analog solutions have trouble with at frequency extremes.