7-segment display driver question

Question

I believe I'm having some issues interpreting an assignment for my Digital Systems class. What I've done so far is make the segment table for the display, make a truth table for A-G, k-maps for A-G, Logisim diagram for a normal 3 to 8 for reference, and a Logisim diagram for the equations from the k-maps.

The assignment says that, for the 7-segment display, I need to "Implement the circuit only in Logisim/Circuitverse using a 3-8 decoder (built with AND gates and NOT gates), OR gates, and a 7-segment display driver." I've attached some screenshots of the work I've done so far for reference. I'm unsure if I need to take the normal 3 to 8 decoder and figure out a way to use a OR gates to output correctly to the 7-segment. Or do I need to derive the equations like I've done with the k-maps? Like a 7-segment decoder? Below is my work, the language of the assignment is what's really boggling me. Do you think that I've done it correctly already? I'm not looking for the answer to the question, but rather if I'm on the right track or not.

Answer 1

The circuit you made with the k-maps will work, but in the instructions it says to use a 3-8 decoder and OR gates. Whether or not your calculated solution will be valid for your assignment, is something you should ask your professor.

However, is also possible to drive a 7-segment using the 3-8 decoder and OR gates; if that is what you were wondering. I will not demonstrate how to here though, per your request of refraining from directly answering the question.

Answer 2

I did find a minimization error. See below.

some initial thoughts

A 7447 7-seg decoder uses 4 binary inputs, not 3. But I take it that this is to be only have 3 binary inputs and works only for 0 to 7. (No 8 or 9 is available.)

Also, I think I see in the problem statement that you aren't supposed to actually use a 3-to-8 decoder module, but instead you are supposed to build a 3-8 decoder out of AND and OR gates, with NOT allowed.

This leaves open a question in my mind. A natural assumption that experienced designers would make is that a 3-to-8 decoder is a very specific thing. But, technically, I could make a 3-to-8 decoder that produces A-to-G outputs for a 7-segment display and add an 8th output that is always '0' or always '1' and it would still be a decoder and more specifically it would be a 3-to-8 decoder in every possible meaning of the phrase. Just not the 3-to-8 decoder that one would normally think of when seeing the phrase. Still, I could make a very strong argument that this term allows my specific interpretation in this specific case.

So this leaves me not wanting to go down that rabbit hole and to instead drill in on your k-maps.

k-maps

In looking over your k-maps, I believe I may have found an error. Here's the table I used:

The above matches your table. (Well, I copied it from your table so I hope so.)

Here's the error. It's C's table:

So, the logic here is \$C=S_1 + \overline{S_2} + S_3\$. That's the only error I found.

There is another note, though:

Here's another way to see G:

That's not better than what you did (which is correct.) It's just another way to see it done, in case it helps.

(I used Neemann's Digital software to produce the above table and k-maps.)