AT25SF081 SPI Flash SO start and end timing

Question

I am now looking into the Figure 11-1 Read Manufacturer and Device ID Signal.

Say my code correctly clocks in the relevant OPCODE on SI.

However, maybe then the software waits a little too long (or not long enough) to begin reading data from SO. Or similarly, for instance, if the final CS to high command is made a little late, or early.

In these situations, will the entire operation be incorrect and no data will be readable? Or will there be correct data in the SO line that can be read, and perhaps only the start and end bits will be incorrect?

Answer 1

From section 4. Device Operation:

The AT25SF081 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master.

The software on your host controller drives the input pins to the Flash device: CS, SCK and SI. If the host shifts in the OPCODE byte, then it needs to wait a while for some reason, the host can keep CS low and stop toggling the clock line for a while until it is ready to start reading bytes. As long as CS stays low, the Flash needs to wait for clock pulses before it outputs the ID bytes. The Flash will not cancel the command in-progress.