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I am using the LP38693SD-3.3/NOPB (datasheet) power converter to step down +5V to +3.3V. I used the WEBENCH power designer tool from TI for the schematic and I chose the input and output capacitors based on the recommendations from the datasheet. My questions are as follows:

  1. Will I run into problems if I connect EN pin to Vin pin through a resistor? Again, this schematic was generated by the WEBENCH power designer tool from TI, but in the datasheet even though it says under 8.3.1 Enable (EN) "If the application does not require the Enable function, the pin must be connected directly to the IN pin." just a little further down under 8.3.3 Foldback Current Limiting it's a CAUTION which I don't really understand(see screenshot bellow).

  2. Did I choose the input and output capacitors correctly? In the datasheet it says that the output capacitor needs to have an ESR between 5-500 mΩ. The issue with the capacitor recommended by TI in the BOM list is that it has an ESR of only 1 mΩ, so it doesn't respect the recommendations from the datasheet. Since the input capacitor doesn't have any requirements when it comes to ESR or capacitance (it only needs to be at least 1uF and no more that 10 µF because I am using an USB port at the input of the power converter), I chose the same capacitor(GRM31CR71H475KA12K datasheet) for the input and output. The capacitor has a minimum of 5 mΩ at ~2 MHz(see screenshot below), but from my understanding if the frequency is not specified in the datasheet of the power converter where it talks about the ESR of the output capacitor, we should assume a frequency of ~100 kHz to max 1 MHz, so this capacitor should be well suited for the output. Also it has pretty good DC bias and temp characteristics(see screenshots below).

  3. Does the EP pin refer to the 'exposed pad' and should it be connected to GND? I couldn't find any reference to this pin in the datasheet.

My schematic:

enter image description here

TI's recommended schematic:

enter image description here

Caution:

enter image description here

ESR of the capacitor:

enter image description here

DC bias characteristics:

enter image description here

Temperature characteristics:

enter image description here

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  • \$\begingroup\$ were you unable to find a 1uf capacitor? \$\endgroup\$
    – SnappyRiffs
    Commented Nov 19 at 22:39
  • \$\begingroup\$ @JadonJung Hi! I assume you are referring to the Cin capacitor. In the datasheet section 9.2.2.3 Input Capacitor, it states: "An input capacitor is required for stability. TI recommends that a 1-µF capacitor be connected between the device's IN pin and GND pin (this capacitance value may be increased without limit)." To optimize the BOM and ensure a minimum of 1 µF capacitance at the LDO input, I selected the same capacitor for both the input and output. This approach simplifies the design and ensures compliance with the stability requirements specified in the datasheet. \$\endgroup\$
    – Robert
    Commented Nov 19 at 22:51
  • \$\begingroup\$ the BOM does not matter because that is what pcb manufacturers use to find the right components for the pcb, if you are willling to have the manufacturer make the pcb for you. there is no software that really uses the BOM \$\endgroup\$
    – SnappyRiffs
    Commented Nov 19 at 22:57
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    \$\begingroup\$ @JadonJung sorry for the misunderstanding, English is not my first language. By "optimize the BOM" I meant instead of having to buy 2 different capacitors for the input and output I chose the same capacitor for the sake of simplicity since the input capacitor doesn't really have any requirements besides having a capacitance between 1uF and 10uF (I have the VBUS line from the USB connected to the input of the LDO so I cant exceed 10uF on the input). \$\endgroup\$
    – Robert
    Commented Nov 19 at 23:11

2 Answers 2

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  1. There shouldn't be any issues using a resistor here, but if you aren't using the enable function, I would just tie it directly. One less component on your BOM. My best guess for why there's a resistor on the webench example is because you might want to use a pull-up resistor for power sequencing purposes; it's very common to chain one power supply's PGOOD (which is typically open-drain) to another's EN.

  2. It is odd that they would give a recommendation that goes against the datasheet. I'd follow the datasheet here and use a higher-ESR capacitor on purpose—the downsides are small. You can also just put a few mΩ resistor in series with the capacitor. Note that the capacitor you've chosen has a minimum ESR of about 3 mΩ over the range of about 300 kHz to 1 MHz. The minimum impedance is about 5 mΩ at 2 MHz, but that's not the same as ESR.

  3. EP universally means exposed pad, yes. Follow the datasheet recommendations; usually the exposed pad should be connected to ground, but some unusual chips require it to be connected to something else. In this case, the datasheet says it should be connected to ground, so connect it to ground.

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  • \$\begingroup\$ Thank you for your response! In this case, I’ll remove the 10k resistor. Also, I appreciate you pointing out that I confused the ESR with the impedance. I’m not sure how I missed that. \$\endgroup\$
    – Robert
    Commented Nov 19 at 13:31
  • \$\begingroup\$ As a test engineer I love those resistors (and I'm really unhappy if they are left out because this limits the coverage of an ICT...) Functionally it's not necessary but I'd still suggest to let it in. You never knwo when you need to use the EN pin for example for debug purposes. If you put in a 0 Ohm, you can remove it. If you put in a few kOhm, you can just pull it to GND for tests. \$\endgroup\$
    – kruemi
    Commented Nov 19 at 14:55
  • \$\begingroup\$ @kruemi Thank you for the suggestion! Just to clarify, are you suggesting that I should keep the 10k resistor in place to allow the EN pin to be temporarily pulled to ground during testing, in case I need to disable the voltage regulator? \$\endgroup\$
    – Robert
    Commented Nov 19 at 18:10
  • \$\begingroup\$ @Robert yes. Every point you have in your circuit where you can either disconnect a signal or inject a signal might come in handy when debugging (yes, it's my job to find faults in circuits with automatic equipment but also manually, so I'm probably biased). I also suggest at least one testpoint on each signal and 3 fiducials per side. :D \$\endgroup\$
    – kruemi
    Commented Nov 20 at 6:15
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With regard to the EP, the datasheet uses a different name:

The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (that is, GND). Alternately, but not recommended, the DAP may be left floating (that is, no electrical connection). The DAP must not be connected to any potential other than ground.

So they "strongly recommend" it be grounded.

Leaving it floating is asking for potential trouble- for example the unknown effect of a possible short due to assembly issues.

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  • \$\begingroup\$ Thank you very much for the clarification; I greatly appreciate it! \$\endgroup\$
    – Robert
    Commented Nov 19 at 17:53

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