I am trying to control a serial dataflash memory through an mbed. It is an AT45DB021B and the datasheet is here. It has a reset pin that I have wired to the mbed so that a software reset can be done. I heard that a software reset makes things easier so that a hardware reset, i.e. shutting off power and turning it back on, is not needed. I noticed that when I do a hardware reset, whatever is in the buffer is overwritten by random values. However, when I do a software reset, the buffer is unaffected. Nothing seems to change on a software reset. Is this normal?


5 Answers 5


Yes this is normal. If you do a hard reset(random powerup) you can be pretty sure that the buffer will be some garbage. If you do a soft reset the contents should be the same as before. Sram is designed to behave that way. But it depends on the design of the architecture. If the internal hardware is desinged in such a way that, on receiving a reset signal, the power to the RAM to be removed. Then, in that case, the contents of the RAM will be cleared on the reset.


After a power-on reset there's no guarantee as to what's in your buffer. It may be the same as what was in it before, or all zeroes, or all ones, or a checkerboard, or most of the opening sentence of "A Tale of Two Cities", or anything else; it may be consistent, or random, or mostly consistent except for the third Tuesday of months containing the letter "a". Unless specified otherwise, it's probably wise to figure there's no guarantee of buffer contents after a soft reset. The proper approach is to assume that the buffer is going to contain whatever data would be most vexing to you, so you should be prepared to accept anything that might be there.


The reason memory and other chips have reset lines is not neccessarily to "clear" them, but to to disconnect them from the bus during low power states.

The problem is that, during power-up and shutdown, the strobe, address and data lines are still connected to the bus while power is rising from 0v to Vcc (or draining away), and this may manifest as digital noise that causes random "garbage" to be written to memory during bootup. This is especially problematic for memory-mapped IO devices, and flash memories.

You can use a "brown-out reset" chip to ensure that your device is held in RESET state until power has stabilized and the bus values can be trusted. Many modern microcontrollers have built-in brown-out detectors.


Datasheet covers this:

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level

So you don't lose buffer values but any operation in progress is stopped and the state machine is reset. So the data in the buffer is invalid (does not line up with current state and may not line up with whats actually in flash, it should be treated as garbage).

If you trip the software reset while a write or read from flash is occurring the operation stops and upon release of the software reset the chip is in its default state. This means that the software reset can corrupt flash data without changing the buffer values. When you write to the flash you have to make sure you allow enough time for the chip to actually write the data to the flash before using the software reset or your data will be not make it to the flash. These times are listed in section 8.2 of the datasheet.

Strictly speaking it is also not safe to read from the data buffer as if it were valid after a software reset, you must re-issue a command to copy data from flash to the buffer before you can read it and be assured that it is valid (equivalent to whats actually in flash).


The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally


When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a highto-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started

So there is no need for an external controller to bring the chip online on power up. Unless your power on operation takes more than 20ms to stabilize supply voltage you shouldn't have any power on garbage issues.


In general, no, a reset is not the same as a power cycle. You have to analyze the system on a case by case basis to determine what happens on a system wide and/or localized reset. From Mark's answer it sounds like you are fine for this target, press reset and not have to power cycle. Saying that before deploying or releasing a version of software though, test it using power cycles as well.

With sram or dram. If you dont lose power and the reset is short enough the memory may very well look like nothing changed, but dont rely on that. Some systems, dram in particular, parity checked, ecc checked memories will go through an initialization process which can include wiping out the memory. Unless the system was designed to preserve the memory through a reset, do not rely on it being the way you left it. Programs should always write before they read a memory location (or the location should be written by someone/something before it is read the first time) anyway.


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