How to find the earliest edge

Question

        ______
A _____|      |________

         ______
B ______|      |_______

Which edge arrives first?

I have two digital pulses that arrive at almost the same time, and I need to determine which pulse arrived first. I need to resolve to ~500ps, i.e. the pulses may arrive 500ps apart and I still need to be able to resolve which one came first. The pulses are the exact same width, they are wide (~10us) relative to the edge timing, and the period of the pulses is about 20ms.

Most of what I've come up with (anything flip-flop-based) doesn't work due to prop delays.

Since what I ultimately want to do is align the pulses, i.e. reduce the delta to 0, I thought about XORing the two pulses (theoretically producing an even shorter pulse the width of the delta) and then minimizing the width of the XOR'd pulse by adjusting the delay of one of the channels. Unfortunately most of the pulse is eaten alive by the rise/fall times of most logic (even PECL is questionable), so it's hard to get a large enough signal to process (peak detect with a diode, R and C and minimize the resulting voltage).

Any other ideas? I'm going to start looking at PLLs next, though I'd rather not if there's something simpler...

Answer 1

Can you put the two into a differential amplifier? Both low or high would be 0 V out. One high before the other is a positive pulse, the opposite situation is a negative pulse. Not sure if that would respond fast enough, or if there's any delay from one input to the other.

Answer 2

My suggestion would be something like this.

The first pulse that arrives pulls the Drain of the FET low, and on the same time blocks input from the second pulse. So the FET's Drain that goes low (during the 10uS pulse high), is the one at which the pulse arrived first.

At those pulse speeds, you are probably going to need some matching on the Gate pin, to avoid the Gate-capaticance having too much effect and further avoiding reflection.

EDIT: there needs to be schottky diodes on the wires between gate and drain, to block the bias from flowing from VCC to gate.

Answer 3

(1) COMPARATOR BASED

The Analog Devices "Ultrafast SiGe Voltage Comparators" ADCMP580/ADCMP581/ADCMP582 look suitably fast enough for the task - datasheet here

Rise and fall times !!!
Fast enough?

With the Analog Devices "Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators ADCMP572/ADCMP573" - datasheet here close behind.

Neither especially cheap :-( - over $20 each in small quantities at Digikey,

The '580 shoes an application with a tolerably good eye diagram at 7.5 Gbps!

'580 - Some specifications:

• 180 ps propagation delay
  25 ps overdrive and slew rate dispersion
  8 GHz equivalent input rise time bandwidth
  100 ps minimum pulse width
  37 ps typical output rise/fall
  10 ps deterministic jitter (DJ)
  200 fs random jitter (RJ)

  and

  −2 V to +3 V input range with +5 V/−5 V supplies
  On-chip terminations at both input pins
  Resistor-programmable hysteresis
  Differential latch control
  Power supply rejection > 70 dB

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(2) GATE BASED

Implementing X NOT.Y gives you a signal that:

• If X goes high first

  Goes high an AND delay after X goes high and goes low again an AND and an INV delay after Y goes high.

• If Y goes high first

  Goes high and AND and an INV delay afer Y and low again an AND delay after X goes high.

This assymmetry is "not nice" and MAY give confusing results under some timings but allows you to use basic gate delays rather than flipflops.

By inverting to the equivalent NOT.X Y you seem to eliminate the transient false state. (Needs more thought).

Answer 4

I'm not exactly sure what you are trying to do, but measuring charge time on a capacitor might work.

For example you have a current source which charges the (very stable, e.g slver mica or similar) capacitor up. When a pulse arrives a second stronger current sink discharges the capacitor very quickly, and then you measure the time taken to charge up again. The current ratios will depend on the counter clock rate and the resolution you want to achieve. Say you have a 100MHz clock and a 1000:1 ratio, then the resolution will be 10ns/1000 = 10ps.
You would have to adapt it to meet your requirements, e.g. arrange it so the input is triggered when one line is at 1 and the other 0 (maybe on the rsisng edge too)

Here is a diagram (the signal input switches I2 on the left):

There are also ICs that can probably do the job, such as the TDC series from Acam. I would expect them to be quite expensive though.