Efficiently decoding a four bit input pattern into one of 16 twelve-bit output patterns

Question

I have a four-bit input pattern. I have 16 distinct 12-bit output patterns. Many of these output patterns have a bits which are set in 2 or 4 of patterns.

If I (arbitrarily) assign each pattern to a four-bit number, I can use various online Karnaugh map tools to generate logic circuits.

This arbitrary assignment of patterns to four-bit numbers adds unnecessary constraints to the problem.

Is there a way of solving this, to give the best pattern<->number assignments, other than by brute-forcing all 16! orderings?

(Where "best" is the pattern<->number assignment which requires least logic to decode the four-bit input one of the 12 bit output patterns.)

Update:

Here are the bit patterns I want to decode a 4-bit numbers to:

0  0  0  1  0  0  0  0  1  0  0  0
0  1  0  1  0  0  0  0  1  0  0  0
0  0  0  0  0  0  1  0  1  0  0  0
0  0  0  0  0  1  0  0  0  0  0  1

0  0  0  0  1  0  0  0  0  1  0  0
0  1  0  0  1  0  0  0  0  1  0  0
1  0  1  0  1  0  0  0  0  1  0  0
0  0  0  0  0  0  1  0  0  1  0  0

0  0  0  0  0  1  0  0  0  0  1  0
1  0  0  0  0  1  0  0  0  0  1  0
0  0  0  0  0  1  1  0  0  0  1  0
0  0  0  0  0  0  1  0  0  0  1  0

0  0  0  0  0  1  0  1  0  0  0  0
0  0  0  0  0  0  0  0  0  0  0  0
0  0  0  0  0  1  1  1  0  0  0  0
0  0  0  0  0  0  1  1  0  0  0  0

It does not matter which four-bit number decodes to which 12-bit pattern, provided there is a one-to-one relationship.

What are the fewest logic gates which will do the job?

While solving the above may be marginally useful, it is the general solution that I am looking for.

Answer 1

You can use an SRAM or a PROM for this. 4 input bits, 12 bits wide. Store your patterns in the memory, use the 4 input bits as the address.

There are 16 word SRAM ICs for this purpose. They would be useless to store "real" data, but are designed for arbitrary lookup tables and implementing simple logic.

Answer 2

You have three options:

1. Use a Lookup Table, as pointed out by @Olin and @Pipe. Given how small it is (16 words) you could easily do it with one or two parallel memory ICs. For example an EEPROM would work.

2. Determine the logic required. This would be done by building 12 Karnaugh maps, each of which has four inputs (your 4bit number), and determines the logic required for 1 of the output bits (hence you need to make 12 maps). You can then do simplification of the logic and see what you can come up with. However in all likelihood you will need many more ICs then just a simple memory. I can't give you an estimate of how many it would be as you haven't posted what your output patterns look like.

3. Use a microcontroller. Yes it seems like a weird idea, but if you are running something slowly and don't mind a high propagation time it can work. MCUs are so cheap nowadays and have everything they need to run built in (internal oscillator, etc.). You would only need one with 16 I/O pins (4 for inputs, 12 for outputs), and then write a simple program which constantly reads the inputs, converts it using a lookup table and writes it to the outputs. That would be a single 20 pin IC - ATTiny2313's for example cost barely $2. I'm sure there are cheaper ones too.