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I have an op-amp circuit that has a block of dip switches that can be used to configure the gain of the circuit. We have had an unusual failure in the circuit that appears to be related to changing dip switches while the unit is powered on. This failure only seems to occur on occasion.

My suspicion is that the issues is caused by the switches being set they pass through a state such that no switch is turned on but have no evidence at this. In addition I would that expect that if all switches are left open this is effectively becomes a voltage follower and should try to drive the voltage to zero volts.

This is a simplified version of my schematic OPA1 is supplied from +- 15V rails, Input voltage is +-10v In- is connected to zero volts in a separate section of my circuit. The output load is a second amplifier stage and would present a load of approximately 100k

schematic

simulate this circuit – Schematic created using CircuitLab

Is there anything that adjusting these switches could do to destroy my op-amp to the extent it releases the magic smoke and leave a small crater in the surface of the op-amp.

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  • \$\begingroup\$ What you show indicates the (+) input is common ground for signal in and out. Is this correct? \$\endgroup\$
    – user105652
    Commented Jul 13, 2016 at 3:25
  • \$\begingroup\$ Yes, the stage after this is a bipolar V to mA stage. The output of that stage is the signal that goes into the outside world and is not referenced to in- \$\endgroup\$
    – Hugoagogo
    Commented Jul 13, 2016 at 3:28
  • \$\begingroup\$ Why wouldn't you put a big resistor to gnd, like 10MR or so? \$\endgroup\$
    – user76844
    Commented Jul 13, 2016 at 4:19
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    \$\begingroup\$ Is your op-amp a unity-gain stable one? \$\endgroup\$
    – The Photon
    Commented Jul 13, 2016 at 5:05
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    \$\begingroup\$ Decide the minimum gain you want and hardwire the appropriate resistor in. Compute all the other gains as resistors in parallel with that one. \$\endgroup\$
    – user16324
    Commented Jul 13, 2016 at 13:23

2 Answers 2

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The crater and magic smoke release is the best clue here. I've had parts returned with a crater hole in a past life as an applications engineer. This is a very strong indicator that you are causing a latchup condition in your opamp. This can happen by either a voltage spike on its power rail, or more commonly, by driving one of the input pins above its positive supply or below its negative supply.

This wikipeda page explains latchup, though it doesn't clearly explain the trigger mechanism. This TI white paper explains it in much greater detail.

A latchup can be triggered by a voltage spike on the power rail, or from driving the input or output beyond the power supply voltage (below GND or above V+) such that enough current flows to trigger the parasitic thyristor structure inherent in CMOS devices.

For example, lets say you have a long sense cable on the opamp inputs. You've decoupled it with ceramic capacitors to filter the noise like a thoughtful engineer. What you may not realize that hot plugging this cable will result in LC ringing (made worse by low-ESR cap like ceramic) that greatly exceeds your supply rails and trigger latchup in the circuit sensing this cable. This is a common culprit. I have scope plots of USB VBUS at the device end ringing to 9 Volt peak when plugged into a PC with a 6 foot cable. Overshoot, noise pickup, LC ringing, etc. all must be designed for when dealing with cables.

To reduce the likelyhood of latchup, you can put series resistors in your inputs. A likely culprint is the + input of the opamp in your circuit. A 1k or greater resistor should do it.

Note that it is not the input overvoltage or undervoltage that damages the device in a latchup situation. The over- or undervoltage momentarily drives current into or out of the IC input to the point that it turns on the parasitic thyristor inherent in all CMOS devices. Thyristors are current triggered. This parasitic thyristor then causes an internal short of the supply rail to GND. If the transistor happens to be small, then you might just see supply current increase but the circuit functioning normally or only somewhat impaired. (You would have to remove power to reset the latchup.) But if the transistors getting turned on are large, then a very large current will flow and will damage your IC from thermal stress.

By inserting a series resistor on IC inputs exposed to possible over/under voltage, you reduce the current below what may trigger the parasitic thyristor.

It also sounds like the opamp is connected to a high current capable power supply. You can also help alleviate the problem by putting a current limiting resistor in the supply of the opamp especially since it does not draw very much current. If the latchup occurs, the current limiting resistor will limit the supply current and prevent device damage. Also, the supply current during latchup will probably now be too small to maintain the latch condition. Note that you should put a decoupling cap on the opamp to maintain stability. So maybe 100 Ohms and 0.1 uF at the opamp. This supply series resistor would also definitely help if the latchup is being caused by voltage spikes on the power rail by limiting the latch current.

I hope that helps find your culprit, -Vince

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  • \$\begingroup\$ Thanks for the detailed answer, I have a few questions though. To add a bit more background the input to this circuit comes from an analog output on an industrial controller, we have done testing on this previously and it has great regulation and transient response. The differential input signal goes back to the plug on the controller and is connected to internal ground there. This connection between devices is an approx 300mm ribbon cable that is never hot plugged, the only thing that is being changed while powered up is the dip switches and the input signal. \$\endgroup\$
    – Hugoagogo
    Commented Jul 13, 2016 at 8:27
  • \$\begingroup\$ For what reason do you suggest the +input is a prime candidate and is 500mA with a couple hundred microfarads of low ESR filter caps considered a large supply. (The op-amp also has 0.1+10uf locally.) \$\endgroup\$
    – Hugoagogo
    Commented Jul 13, 2016 at 8:29
  • \$\begingroup\$ On the "high current supply", was a guess. Basically, the supply needs enough energy supplied in a very short time (very high current peak) to vaporize the IC's metalization and semiconductor to blow a crater in the package when latchup occurs. Even though yours is only 500 mA, the low ESR caps would do it (supply high current peaks) \$\endgroup\$ Commented Jul 13, 2016 at 16:42
  • \$\begingroup\$ Re: suspecting input side, hmm... sounds like you did a good job verifying that it is clean. How about the output side, when SW4 is switched on and off? Does the output have some capacitance that can get charged when SW4 is in the up position which would get dumped into OPA1's output when SW4 is moved to the down position? Since you're blowing craters in the IC, it would make sense that the latching is occurring on a very large CMOS FET pair. The biggest transistors on that IC would certainly be the push-pull output. \$\endgroup\$ Commented Jul 13, 2016 at 16:50
  • \$\begingroup\$ I just realised my circuit as posted might not be 100 percent accurate, the second stage is before SW4. I have updated the schematic to reflect this (I unfortunately can't include a full schematic). The output of the first stage effectively has 47k ohms on each of its input and would have a total capacitance definitely less than 0.1uF. I would imagine worst case to have .3mA steady state in or out of the output. \$\endgroup\$
    – Hugoagogo
    Commented Jul 14, 2016 at 1:16
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Could be that there is bounce on the switch. Use an SR latch as a switch debouncer

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    \$\begingroup\$ An SR latch in unlikely to be of much use in an analog circuit such as this. \$\endgroup\$
    – brhans
    Commented Jul 13, 2016 at 12:25

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