VHDL define range as previously defined range + offset

Question

Is there some way in VHDL to define a range as a previously defined range plus some offset? Below is an example of what I would like to do but I can't figure out the correct way of going about it. In this example the FIFO's din/dout are 47 downto 0.

constant X_DEPTH        :   integer := 8;
constant Y_DEPTH        :   integer := 8;
-- Expected range 7 downto 0
subtype X_MAX_RANGE is natural range (X_DEPTH-1 downto 0);
-- Expected range 15 downto 8
subtype X_MIN_RANGE is natural range X_MAX_RANGE + X_DEPTH;
-- Expected range 23 downto 16
subtype Y_MAX_RANGE is natural range X_MIN_RANGE + Y_DEPTH;
-- Expected range 31 downto 24
subtype Y_MIN_RANGE is natural range Y_MAX_RANGE + Y_DEPTH;
-- Remaining bits (Expected 47 downto 32)
subtype REMAINDER is natural range 47 downto ???; -- Y_MIN_RANGE max + 1
signal dummy1,dummy2    :   std_logic_vector(REMAINDER);

begin

    FIFO_inst : entity work.FIFO
    PORT MAP
    (
        clk     => CLK,
        srst    => RESET,
        din(REMAINDER)          => dummy1,
        din(Y_MIN_RANGE)        => y_min,
        din(Y_MAX_RANGE)        => y_max,
        din(X_MIN_RANGE)        => x_min,
        din(X_MAX_RANGE)        => x_max,
        wr_en   => wr_en,
        rd_en   => rd_en,
        dout(REMAINDER)         => dummy2,
        dout(Y_MIN_RANGE)       => y_min_out,
        dout(Y_MAX_RANGE)       => y_max_out,
        dout(X_MIN_RANGE)       => x_min_out,
        dout(X_MAX_RANGE)       => x_max_out,
        full    => full,
        empty   => empty,
        valid   => valid
    );

Answer 1

You can use attributes as 'right, 'left, 'low and 'high to generate one range from another :

For example :

  subtype X_MIN_RANGE is natural range X_MAX_RANGE'low TO X_MAX_RANGE'high + X_DEPTH;

For more elaborate operations, you can also define functions (with integer parameters) that will be evaluated during synthesis as long as inputs are constants:

FUNCTION tweak(v : natural) RETURN natural IS
BEGIN
  RETURN 2*v + X_DEPTH;
END FUNCTION;

subtype Y_MAX_RANGE is natural range X_MIN_RANGE'low TO tweak(X_MIN_RANGE'high);

Alas, VHDL is not "functional" enough to allow returning generated types or ranges fron functions.

Answer 2

I want to make this one perfectly clear, so I'll keep it short. VHDL describes hardware, so what you are asking for is a piece of hardware to run off previous values. These stored values of which you speak are memory. So to do what you want I would suggest a latch, where based on a condition, you latch a value somewhere to act as a stored value, and then work off the output from the latched memory.