Output Drift of an operational Integrator

Question

R = 1k and C = 0.1 uF

1. In practice, the output of an operational amplifier integrator will (drift) until it saturates at a value close to one of the supply voltages, even when the input voltage (Vin = 0). Why does this happen?

2. How can we prevent the drifting?

I found the answers on Wikipedia but I couldn't analyse them logically.

Answer 1

Even for Vin=0 the output voltage will ramp up to the maximum (supply rails) due to the finite output offset voltage (input offset times open-loop gain). This cannot be avoided for stand-alone integrators. In many cases, a resistor in parallel to the feedback capacitor can limit this unwanted DC output. The corresponding DC output voltage is Vin*Acl (closed-loop DC gain). However, at the same time, the integrating function is somewhat disturbed (for low frequencies) because the integrator has become a first order lowpass. hence, a trade-off is necessary regarding the resistor value (as large as possible and as low as necessary).

But note, that this problem does NOT exist in case the integrator is used as part of an overall negative feedback loop (as is the case for many control loop sysytems)..

Answer 2

How can we prevent the drifting?

If you journeyed to the end game and ignored the capacitor (because all it does is slow down the inevitable), to ensure that the output of the op-amp remained at 0V (mid-rail), you have to overcome: -

• The input offset voltage problem
• The input bias current problem
• The input offset current problem

Then you have to ensure that these problems remained constant and that they didn't move with temperature.

To overcome the input offset voltage problem, you have to produce a small dc value from Vin equal to the op-amp's input offset voltage. Once you have done this you have to ensure that input bias currents in each of the op-amp's inputs had equal effects. This is usually done by putting equal values of resistors in each connection and, because -Vin has a resistor of "R" then a value of "R" has to be placed in series with +Vin.

Once this is done, you have to cope with the mismatch of input bias currents (called input offset current) and adjust the resistor formerly called "R" by an amount to make the voltage difference that each input resistor produces zero.

After you have done all of this, you have to manipulate the resistors in such a way as to counter temperature changes in these offsets currents and, manipulate the small DC value (from Vin) because input offset voltage also changes with temperature.

If you do all of the above, whether you have a feedback capacitor or not, you will maintain the output at 0V (ignoring noise voltages present at the inputs and long term drift related to aging and mechanical induced hysterisis). You will also have to counteract the effects of resistor values changing with time and temperature as well as the leakage current of the capacitor (and it changing over time).

Why does this happen?

This should be clear now.

Answer 3

**It assumes you are aware of the limitations of your OpAmp;**

• Common Mode input range MUST be allowed to Ground for single supply if this is the case. Or use a split supply.
• Vio (input offset voltage) (dVout/dt = Ic/C= Av*Vio/R1*C)
• Iin ( input bias current * R1 adds to Vio) Otherwise the output will drift.

Get specs for Vio and Iio and add R to Vin+ to match R to null Iin offset voltage.

Then use fixed R and small trimpot to tune 0uV offset at Vin+. Use very low Vio offset Op Amp with Rail-rail output (optional)

then add 74HC4066 switch to dump Vcap to reset (optional or use MOSFET for single supply)

• most important use only plastic caps for low leakage Caps as ceramic is leaky
  • e.g. polypropylene, polyester , "polyanything" or teflon or silver mica for tiny caps

then you might be able to sustain 0V for a few minutes...after all this