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Why higher frequency processors use more power?

A higher frequency processor would solve the task in less time, thus increasing idle time and thus reducing power consumption.

This would compensate the fact that it uses more power.

What's wrong in my reasoning?

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  • \$\begingroup\$ Nothing except that the speed ratio might be not the same as the power ratio.. But a typical processor is not solving just one task. It's a pretty busy guy. \$\endgroup\$ – Eugene Sh. Dec 9 '16 at 18:56
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    \$\begingroup\$ Nothing wrong with your reasoning. In embedded systems it's a very common way to manage power. \$\endgroup\$ – The Photon Dec 9 '16 at 19:06
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If you have a processor which can operate at two frequencies when it isn't idling, say f1 and f2, then there will be a different power consumption per frequency, as explained in other answers here.

The power consumption depends on the frequency in a non-linear fashion, so you might have:

f1 100MHz 1W
f2 200MHz 2.5W

If you have to execute 100 million instructions and the processor can do one instruction per clock cycle, you can do it at f1 or f2:

energy used at f1 = 100M instructions/100MHz / 1 (instruction/cycle) * 1W = 1J energy used at f2 = 100M instructions/200MHz / 1 (instruction/cycle) * 2.5W = 1.25J

So at f2 the execution is completed in 0.5s instead of the 1s at f1, but it took more energy.

However, there are other considerations in a computer system: for example, if you can get a disk drive into an idle state sooner because the processing has finished then the savings from the disk drive power consumption may be greater than the extra energy used in the processing. Another example: if the user can finish their work in half the time, they can shut down the computer and save on energy used to run the monitor.

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You are assuming that power consumption is a function of time but not frequency.

If the logic gates have some gate capacitance, then as you increase the frequency at which you switch them you increase the number of times you charge and discharge the capacitors per unit time. Which therefore increases power consumption.

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1) You're not wrong. Higher frequency results in solving problems faster. The limit becomes if you try and solve it in virtually 0 time, you heat up the part so hot you let the magic smoke out. That magic smoke is expensive and we'd rather not let it out, so instead, we lower the frequency to allow the CPU to last for 5-10 years. That means our limit isn't frequency, but the thermal limit of the part. And solving the problem faster by increasing frequency can only be done up to the point of the thermal limit.

2) The other thing is if the part can solve problems faster, people inevitably want to use that part to solve more problems. So now it needs to continuously solve problems faster and once again you hit the thermal envelope.

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Switching uses energy. Each time a line switches state the capacitance of that line must be charged/discharged. In CMOS logic this was traditionally the main cause of power consumption.

Modern processors have idle states, so they can significantly reduce (but not eliminate) the switching when they are idle. So by that logic you would expect the average power to be similar for a fast processor than a slow processor. The fast processor would use more power when processing but it would get back to the low power idle state quicker.

But there are other factors. It takes time for a line to settle into a state that can be reliablly detected as the correct value, to increase clockspeed while maintaining correct behaviour we have to deal with this. There are a couple of strategies.

  1. We can reduce the ammount of stuff that happens between a pair of clock edges by adding extra pipeline stages. Unfortunately not only do the pipeline registers themselves cost power, the longer pipeline nessecitates the use of tricks like branch prediction and maybe even out of order execution to avoid unacceptable pipeline stalls.
  2. We can increase the size of the transitors relative to the lines they drive. Unfortunately that means more capacitance on the transitors.
  3. We can increase the operating voltage. This results in the lines reaching an acceptable state faster but also increases the energy lost in each switch.

All of these things cost power.

So all else being equal a faster processor will generally get less work per joule done than a slower one.

This is somewhat compensated by the fact that faster processors tend to be built on newer technology nodes that allow everything to be made smaller and hence more efficient.

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Building on Peter's answer, most processors require a bit more voltage to remain stable at the higher frequencies. This voltage-power relationship is most definitely non-linear.

Think of a basic (ideal) CMOS switch, when on it acts like a wire, when off it acts like an open circuit. Both times the switch is using basically zero power itself. However, when switching you need to charge and discharge the gate capacitances, this takes energy. At a fixed voltage, the energy that goes into charging and discharging the capacitance is constant, e.g. you need 0.5J of energy to charge a 1F cap to 1V regardless of how fast you do it. So that's a fixed loss per cycle.

The interesting things happen when you change the voltage. Now I can't say why many chips need more voltage at higher frequencies, but I can say that the energy stored in the gate capacitances is $$E = 0.5*C*V^2$$ Where E is energy, C is capacitance and V is the gate voltage. Our ideal switching power loss is $$P = E*f\ \ \ or\ \ \ 0.5*C*f*V^2$$ Where P is power and f is frequency. So higher frequencies need proportionally more power, but higher voltages need exponentially more power and because higher clocks tend to go hand in hand with higher core voltages, the power required can rise quite quickly.

Then you've also got things like on-state resistance, non-ideal switches, power loss that rises with temperature (high clock = more voltage = more loss = higher temperature = more lossy circuits = even more loss), static loss (CMOS switches are never truly off and they leak more and more power as the temperature climbs). So there's quite a few reasons that cause power losses in modern chips to be non-linear. Basically anything that increases the power draw and thus the temperature makes everything worse... it's a fine balancing act really.

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For a given CMOS technology and voltage, dynamic power is proportional to frequency, so if a task takes n clock cycles then it will take the same amount of (dynamic) energy regardless of clock frequency. However, for a typical chip there are many complications. For example, for a PIC16F627, the maximum frequency is a function of the supply voltage:

enter image description here

If we need to operate at 20MHz we'll have to give the chip at least 4.5VDC (say 5.0V nominal). Since dynamic power is proportional to voltage squared, if we can operate at 4MHz we could reduce the supply voltage to 2V (say 2.2V nominal) so the energy per cycle will go down by a factor of (2.2/5)^2 or almost 5:1. That's a huge reduction, but it requires making a 2.2V system rather than a 5V system, so it's more than just a coding or crystal frequency decision. Note that the power drops by a much bigger factor (25:1) but it has to run 5x as long to accomplish the same task, so that doesn't count for much.

There are yet other complications- some of the chip power is there whenever the clock is running or various peripherals (watchdog timer, ADC, brownout detection, ADC etc.) are powered. They may take significant time to start up or shut down. The assumption above is that the processor could wake up and do its work and then sleep using almost zero power, but that's not always possible.

So if you are going to analyze what is best you have to consider a lot of different factors.

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  • \$\begingroup\$ Some chips include circuitry to reduce the voltage internally when using certain low-power modes without having to use external circuitry for that purpose. \$\endgroup\$ – supercat Dec 9 '16 at 23:44

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