I'm currently working on a project which features an Analog Devices Blackfin DSP Digikey link. This DSP requires 1.3V to power the core. I plan on having my project be battery powered, thus I'm looking for efficient power regulators.

I've noticed in a lot of schematics that use this chip (and other DSPs in general), the core voltage is typically regulated via an LDO. I understand that LDO regulated power will be cleaner then a switched power supply, but an LDO would be less efficient given that I will be stepping down from 3.3V.

I wasn't able to find anything in the Blackfin datasheet regarding maximum core voltage ripple. So my question: is it 'ok' to use a switched power supply to power a processor core?


Yes, it's done all the time. True, switched supplies can produce more noise, but the efficiency improvement is usually enough of a reason to use them. You just need to make sure you adequately filter that noise before feeding it to the processor.

If your battery supply voltage is such that an LDO is still very efficient, then sure you can use an LDO and it will be a simpler, smaller, and less expensive design. But usually that's not the case.

Also many people aren't comfortable with switcher designs and the necessary noise mitigation required, so they tend toward LDOs. But if done properly a switchmode supply will be fine.

You won't usually see max ripple specs on processor datasheets, but for 1.3V I would probably try to shoot for <5% at full load. If your component selection allows for that you shouldn't have a problem.

You mentioned it was battery operated but that the regulator would be powered from 3.3V. So does that mean you already have a 3.3V regulator? What is the battery type/voltage?

  • \$\begingroup\$ This is good information, thank you. So I plan on having my design support both battery power and 3.3V plugin power. Because it's possible that my board be operated without a battery and just from a 3.3V source, I decided I would derive all power from a regulated 3.3V source. I will likely have a 3.3V regulator on the board to step up the battery voltage (assuming AAA or AA). However, I could imagine using an LDO right after a raw 1.5V battery would be quite easy to implement. Also, I plan on having 3.3V be the primary voltage level for serial, I/O, other ICs, etc. \$\endgroup\$ – Izzo Feb 18 '17 at 18:45
  • \$\begingroup\$ OK right, so if you have a 1.5V battery, you lose efficiency if you step up to 3.3V and then back down to 1.3V, so you could go LDO straight to 1.3V. But on the other hand, you would lose some of the useful battery life once it discharges below 1.1V. If you need to run from both battery or wall power, it might be simplest to use two or three cells if possible and regulate 3.3V from both those inputs. Considering this chip uses a fair amount of current, I still think you would want to use switchmode to go from 3.3V to 1.3V. I also noticed that depending on clock, the min. voltage is higher. \$\endgroup\$ – AngeloQ Feb 18 '17 at 20:10

Since the VDDInt operating characteristics in the datasheet show 1.1 -1.47 V operating range it would seem that providing your ripple does not go beyond those voltages you'd be ok.

Since VDDInt current maxes out at about 100 mA it would seem you could take a hybrid approach and use a 3.3 to say 1.5 V switched mode supply and a linear LDO to go from 1.5 V to 1.3.
There are a bunch of LDO's that supports only 150 mV or dropout voltages, here's one. This hybrid approach would appear to be able to drop your power consumption from about 350 mW to about 170 mW but carries with it an increase in complexity.

  • \$\begingroup\$ That's an interesting idea.. But if a switchmode supply would work, why pursue the hybrid path? Just for assurance? \$\endgroup\$ – Izzo Feb 18 '17 at 18:48
  • \$\begingroup\$ I wouldn't do it (pursue the hybrid) unless the ripple was pushing the operating voltage toward a limit. For example if I was leaving a sleep to active state the VDDInt might jump quite suddenly from just mA or so to close to 100 mA. With an SMPS there will be a dip (depending on switching frequency) ...I might also see a sudden rise as I leave active and go to sleep mode. With a hybrid approach I can buffer the SMPS with output capacitance and let the LDO remove the ripple reducing the work I need to do on the SMPS while remaining within my voltage limits. \$\endgroup\$ – Jack Creasey Feb 18 '17 at 19:31
  • \$\begingroup\$ Because it's often much much easier to design a SMPS that is "close enough" for an LDO to be very efficient. In total, you lose little energy in the LDO and get excellent regulation with low cost, low complexity, low risk and little space usage. \$\endgroup\$ – Marcus Müller Feb 18 '17 at 19:33

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