Is it 'normal' to use a DSP's internal timers to generate lower speed clock signals for audio codec sampling?

Question

I'm currently working on a project that features a Blackfin BF592 processor (datasheet).

I'm trying to interface this DSP with a stereo audio codec (datasheet).

Originally, I assumed that this audio codec would have some high frequency clock signal (i.e. frequency much higher than the sample rate) that would likely be fed from some oscillator circuit. I believed that this input clock would be divided as necessary to get a lower clock signal (e.g. 44.1kHz).

However after looking through the datasheet of this codec, it appears that the expected clock signal inputs are meant to be 'exact' and relatively low frequency (i.e. 44.1kHz-ish). And because this chip is a delta sigma codec, it actually expects two sample rate related frequencies: the actual sample rate clock, and then a multiplier of the sample rate clock to achieve proper oversampling.

Because I plan on sampling at 44.1kHz, with a oversample rate of x32, I will need two clock inputs: 44.1kHz and a 1.411MHz.

So my question: is it standard practice to use a DSPs internal timers to generate these signals? Or would it be more common to have a dedicated IC generate these two signals?

Answer 1

In general you try very hard to avoid adding extra components to your circuit. It's just extra cost, extra board space, more circuits to keep in stock, more that can go obsolete, etc.

In your case, I would definitely use the timers in the DSP, if that's feasible. I have no direct experience with it, but it seems to have three externally accessible timers, so it should work well.

...however

I don't think you have read up on the timing, especially not on the features in the DSP. Your DSP has two serial ports which they call SPORT0 and SPORT1. According to the manual you have linked, each can operate in any of these modes:

• Standard DSP serial mode
• Multichannel (TDM) mode
• I²S mode
• Packed I²S mode
• Left-justified mode

If you read a bit about I²S, you will soon realize that your CODEC actually doesn't have that many clock inputs. It has an I²S port. Your DSP should easily be able to connect directly without having to use any of its timers. The details are described further in the hardware reference.

If you're new to this, it will be very confusing. There's not much to do about that, except practicing, and even then you still have to do the job, it just gets slightly easier the more you've done it.

MCLK

You still have to take care of feeding a valid MCLK. As you can see from Table 1 in the CODEC manual, it doesn't have a 32X oversampling mode. Delta-Sigma converters are strange. Page 9 indicates that whatever you feed on MCLK, it will be internally converted to a clock 256fs. Since you want 44.1 kHz, Table 1 gives you four equally valid options: ~11 MHz, ~17 MHz, ~23 MHz, and ~34 MHz.

This gives you some flexibility. To avoid unnecessary headache, run your DSP at a multiple of any of those, then use one of the timers to create one of the clocks above. Since there doesn't seem to be a quality difference between the options, I suggest generating the lowest multiple: 44100 x 256 = 11.2896 MHz.

I don't even know if the DSP timer can output a signal that high, but it seems to have a decent VCO/PLL, meaning that you can probably even feed the DSP and the CODEC the exact same clock signal, and then have the DSP scale it up internally:

That's a whole nother question though.