I'm currently reading through the datasheet for the 74HC165 8-bit asynchronous parallel-to-serial shift register, and I've a handful of questions about the static and dynamic characteristics described therein:
The recommended operating condition for supply voltage (Vcc) states a typical value of 5V (with a minimum and maximum of 2V and 7V, respectively). Why then, when listing the static/dynamic characteristics such as logic voltages and timings, does the datasheet use Vcc = 2, 4.5, and 7 volts as its conditions for min/typ/max and not 5V?
A few of the timing characteristics have those three, but then they have a Vcc = 5V case which also specifies an output load capacitance (C_L). Why is this, and why for only some of them?
The timings only have minimum and typical periods, but they don't seem to make sense. For example, pulse width (t_W) which as I understand represents the amount of time the pulse needs to be active to allow time for detection, has a minimum of 16 ns and a typical period of 5 ns. The minimum is obviously larger than typical, so what am I supposed to make of this?