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I read the ATX power supply design guide, and I have a question related to the PWR_OK line specifications. In "Table 21. PWR_OK Signal Characteristics" I saw the following: "Logic level high - Between 2.4 V and 5 V output while sourcing 200 μA". My question is: what does this mean exactly? When PWR_OK is high the current will be limited by the PSU at 200 uA, so I will not be able to draw more than that from the PWR_OK line?. Or if I am trying to interface something with the PWR_OK line I should take precautions not to draw more than 200uA?

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You'll most likely have to limit the current yourself. It's under that condition that the voltage is specified. Going higher than 200\$\mu\$A will probably cause the voltage to sag below 2.4V, which is the minimum for a high level in TTL. (I've also seen 2.7V as the minimum, I guess it depends on the TTL subfamily.)

Note that the same table says that "signal type = +5V TTL compatible", and that a low level is specified as < 0.4V. That output level is 0.4V less than the maximum TTL input level for a logic 0. And the 2.4V is 0.4V higher than the minimum for a high input level. This gives a 0.4V noise margin.

If you want to control a MOSFET with the PWR_OK signal, like OP, you'll need a logic level MOSFET, which draws enough current at a low \$V_{GS}\$. The BSG103 may be a good choice; it has an \$I_D\$ of 750mA at a \$V_{GS}\$ as low as 1.5V.

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On second thought the BSH103 may be too good. It has a \$V_{GSth}\$ of 0.4V, which means that worst case you'll have a drain current of 1mA with PWR_OK low. Even FETs with a \$V_{GSth}\$ of 1V typical indicate 0.4V as a minimum value. Can be fixed by using a resistor divider to lower the output voltage from PWR_OK. A 15k\$\Omega\$ + 25k\$\Omega\$ gives you a minimum gate voltage of 1.5V, while the current is maximum 125\$\mu\$A.

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  • \$\begingroup\$ What I am trying to do is to signal to a MCU when the PSU is turned on and PWR_OK is asserted high. So for this I am thinking of using a N channel MOSFET with the gate connected to PWR_OK. The MOSFET should switch on when PWR_OK goes high and switch off when PWR_OK goes low. No high frequency switching is involved. In order to limit the current drawn from the PWR_OK line when the gate is charging, I am thinking of putting a resistor in series with the gate and the PWR_OK line. To limit the current to about 160 μA I should use a 30KOhm resistor (at 5V). Is this a good approach? \$\endgroup\$ – Buzai Andras May 22 '12 at 19:34
  • \$\begingroup\$ Isn't the resistor for the gate to big? Wouldn't is slow down too much the turn on time of the MOSFET? \$\endgroup\$ – Buzai Andras May 22 '12 at 19:35
  • \$\begingroup\$ @Buzai - You don't really need the resistor, the output impedance of the PWR_OK voltage will do. That gate capacitance is not that big. If you do want to use a resistor a 4k7 will do. Make sure your FET is a logic level FET, which gives you some drain current already at the 2.4V. \$\endgroup\$ – stevenvh May 23 '12 at 4:20
  • \$\begingroup\$ Thank you. One more thing. I also intend to put a 100k resistor from the gate to ground to prevent accidental turn-on off the FET. So instead of a 4k7 resistor I was thinking of using only a 1k resistor (the 1k and the 100k will form a voltage divider) to minimize the voltage drop across the resistor in series with PWR_OK and the gate. Are there any disadvantages in doing so? Is this setup ok? \$\endgroup\$ – Buzai Andras May 23 '12 at 14:28
  • \$\begingroup\$ @Buzai - That's good thinking, but I would use a 1M\$\Omega\$ resistor and keep the 4.7k\$\Omega\$. Do you already know which FET you're going to use? \$\endgroup\$ – stevenvh May 23 '12 at 14:45

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