# VHDL D-type asynch flip flop

I just started learning vhdl code and i wrote this code for a D type asynch flip flop. How should i modify my code so that it has a second D-type, with the input to the second being fed from the output of the first?.

library ieee;
use ieee.std_logic_1164.all;

entity FLIPFLOP is
port (
clk : in  std_logic ;
clr : in  std_logic ;
D   : in  std_logic ;
Q   : out  std_logic
);
end FLIPFLOP;

architecture behav of FLIPFLOP is
begin
process (clk,clr,D)
begin
if clr = '1' then
Q<= '0';
elsif rising_edge (clk) then
Q<= D;
end if;
end process;
end behav;

• I would suggest don't modify this code, instead create another entity and instantiate two of these FLIPFLOP entities into that new entity and connect output of the second to the input of first as you want. – sarthak Oct 8 '17 at 18:14
• what do you mean another entity? there can only be one entity in this file – super95 Oct 8 '17 at 18:24
• You can have multiple entities in same file. – sarthak Oct 8 '17 at 18:26
• The way to do this is to create a top block who instantiates two instances of a component. The component instantiated is the D- flip flop you created. Search for components and entities on VHDL – Claudio Avi Chami Oct 8 '17 at 18:49
• is there a way of doing this with creating a second process? – super95 Oct 8 '17 at 18:56

I like to keep shift registers defined as vectors. Doing so helps maintain code in the long run. You'll find that this is only 2 lines longer than what you already had (ie. one line for std_logic_vector declaration, and another line to assign the output).

Try this:

entity dualff is
port (
clk : in  std_logic;
clr : in  std_logic;
d   : in  std_logic;
q   : out std_logic );
end dualff;
architecture Behavioral of dualff is
signal dffs : std_logic_vector (1 downto 0) := b"00";
begin
q <= dffs(1);
process (clk, clr)
begin
if clr = '1' then
dffs <= "00";
elsif rising_edge (clk) then
dffs <= dffs(0) & d;
end if;
end process;
end Behavioral;


RTL:

You can do this in a single process.

Declare a signal q0 and modify the process like below.

process(clr, clk)
begin
if clr = '1' then
q0 <= '0';
Q <= '0';
elsif rising_edge(clk) then
q0 <= D;
Q <= q0;
end if;
end process;


This will compile into two D flip-flops with asynchronous clear and the Q output of the first flip-flop feeding the D input of the second one.