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High-speed serial links such as Gb ethernet, PCIe, Firewire, etc support bit rates that suggest signalling frequencies far in excess of typical clocking speed of typical chips. I am wondering how these signals are processed.

Example: SATA supports up to 6 Gb/s on a single pair of differential signalling lines. This suggests a signalling frequency of the order of 6 GHz, right?

While modern processors clock in the vicinity of this, I do not think SATA chips themselves are clocked so high. - Can somebody enlighten me on the design tricks used for processing such high-frequency signals? Are several bits processed within each clock cycle? If so, how?

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While it is difficult for a whole chip to run at very high frequencies (e.g. 6 GHz), you can run a very small circuit at high frequencies relatively easily. The trick is that you have the bare minimum circuit running at 6 GHz.

To do this, parallel data from inside the sending chip is sent to a serializer, which encodes the data for DC balance and synchronization (8b/10b codes). The data is fed into a shift register, and the shift register is clocked at 6 GHz. At the receiving end, the clock must be recovered from the signal sent over the wire with a PLL, and the PLL recreates the 6 GHz clock that was used to send the data. Using this clock, a shift register shifts in data from the serial line, and then the data is decoded. At this point, the data is ready for use with the internal logic of the chip. This process is sometimes called a SerDes, or a SERialize - DESerialize.

To show how this can work with a chip that has a modest clock frequency, lets simplify the system, and assume that we need to fill a 6 Gbps channel with 6*10^9 bits of data per second. If we have a 32 bit word size in our device, then we could load our serializer (or unload our deserializer). If we fill a buffer with 32 bits of data every clock cycle, then we need to fill it at a rate of (6,000 Mbps / 32 bits = 187.5 MHz) 187.5 MHz. Again, this neglects any protocol overhead, so in practice this could be lower. This is a very reasonable clock frequency for a high performance chip (such as a SATA or PCIe transciever). You could operate at a higher clock frequency to give you more overhead, or operate at a lower frequency by using a wider data bus (64 bits, 128 bits instead of 32 bits).

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  • \$\begingroup\$ Thanks. This really helped. Am I correct in guessing that due to the fact that part of the chip has to be run at very high speeds, high-speed serial data processing can only be done with ASICs? It is impossible to replicate in FGPA or similar without dedicated circuitry? \$\endgroup\$
    – ARF
    Jun 11 '12 at 14:33
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    \$\begingroup\$ @Arik, you wouldn't be able to make a SerDes with the core logic in an FPGA. However, many FPGAs have the dedicated circuitry needed for high speed serial buses, even low cost ones such as the Spartan 6 from Xilinx and the Cyclone V/IV from Altera. \$\endgroup\$
    – W5VO
    Jun 11 '12 at 14:42
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Serial ATA uses an LVDS signal running at whatever the desired bit rate is (1.5, 3, or 6Gbps). From what I recall of the SATA specification it is an AC coupled LVDS pair (and wikipedia confirms this).

To achieve these sorts of data rates a PLL is employed to generate the desired/required clock and a serial shift register is used to transmit the data out across the wire. Likewise on the receiver a shift register is used to turn this stream of bits into addressable words.

When design circuit boards to carry the SATA signals careful attention has to be paid in routing the signals. One of the keep concerns is ensuring impedance matching and equal lengths for the traces.

Edit

I failed to mention that de-emphasis and equalization are often employed to achieve the high data rate serial communications. These same techniques are often employed with FPGAs that support high data rate serial interfaces such as RocketIO and PCI Express.

Edit 2

As mng points out the two logical blocks (transmit and receive) are covered by the term SerDes (serializer, deserializer). One of these blocks (serializer) takes a parallel data source (say a 32-bit DWORD) and shifts it one bit at a time across the wire. This process occurs asynchronously with the main CPU clock (as it is not utilized for this). The clock used for the serialization process is running at the data rate of the serial bus (6GHz for 6GBps SATA for instance). This is a similar concept (albeit entirely different data rates, with the bus being slower than the CPU in most cases) as what is used in SPI and I2C. Additionally as part of the serialization process bit stuffing is often employed. This is done to ensure an equal number of high and low bits appear on the line, and to aid in the clock recovery process.

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    \$\begingroup\$ I think a key word to mention is SerDes. \$\endgroup\$
    – mng
    Jun 10 '12 at 22:35
  • \$\begingroup\$ @tallganglyguy Thanks for this answer. I was however especially interested in how such high-speed signals are processed by chips that appear to clock much slower. I believe your edit points in this direction but it is too abstract for me to understand. The hint regarding de-emphasis and equalization only help if one already knows what those are... Maybe you have a wikipedia link or similar for the novice? \$\endgroup\$
    – ARF
    Jun 11 '12 at 10:03

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