While it is difficult for a whole chip to run at very high frequencies (e.g. 6 GHz), you can run a very small circuit at high frequencies relatively easily. The trick is that you have the bare minimum circuit running at 6 GHz.
To do this, parallel data from inside the sending chip is sent to a serializer, which encodes the data for DC balance and synchronization (8b/10b codes). The data is fed into a shift register, and the shift register is clocked at 6 GHz. At the receiving end, the clock must be recovered from the signal sent over the wire with a PLL, and the PLL recreates the 6 GHz clock that was used to send the data. Using this clock, a shift register shifts in data from the serial line, and then the data is decoded. At this point, the data is ready for use with the internal logic of the chip. This process is sometimes called a SerDes, or a SERialize - DESerialize.
To show how this can work with a chip that has a modest clock frequency, lets simplify the system, and assume that we need to fill a 6 Gbps channel with 6*10^9 bits of data per second. If we have a 32 bit word size in our device, then we could load our serializer (or unload our deserializer). If we fill a buffer with 32 bits of data every clock cycle, then we need to fill it at a rate of (6,000 Mbps / 32 bits = 187.5 MHz) 187.5 MHz. Again, this neglects any protocol overhead, so in practice this could be lower. This is a very reasonable clock frequency for a high performance chip (such as a SATA or PCIe transciever). You could operate at a higher clock frequency to give you more overhead, or operate at a lower frequency by using a wider data bus (64 bits, 128 bits instead of 32 bits).