ASIC chips are hundreds of times faster than traditional chips.

Is it possible to design an entire operating system or application using a full custom ASIC chip?

Based on what I've read I understand ASIC chips are not very flexible so they cannot be re-programmed but what if I do not plan on changing my program in the future and just want to take advantage of the speed increase ASIC offers - is something like this possible or is it limited to relatively simple functionality such as hash functions?

If something like this is possible I have two more questions:

  • What magnitude of speed increase can I expect over traditional CPUs?
  • What could I expect to spend on such a device (I know it could cost about $1 million to design one such chip)



I think there's a lot of confusion surrounding this question but basically I am trying to understand the limitations of ASIC chips. My understanding is that the only limitation of ASIC chips is that the algorithm (or whatever "software") they run is fixed and cannot be changed (somehow the chips are designed to execute a specific algorithm). So if I had an application which is fixed in nature could the application benefit from ASIC technology?

@JRE "An ASIC is hardware. An operating system is software" - how did I imply otherwise?

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    \$\begingroup\$ "Normal CPUs" are ASICs. Edit: You removed the name, but not the misunderstanding. \$\endgroup\$
    – Eugene Sh.
    Jan 18, 2018 at 18:06
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    \$\begingroup\$ The reason an ASIC is fast is because it can do only one thing, but do it very well. An ASIC might be extremely fast at doing a certain encoding, but it can't do anything else. A CPU is quite the opposite of that - it can do a lot of things, but because it can, it isn't extremely specialized in any one of them so will perform a bit slower. Trying to put an operating system on an ASIC defeats the entire purpose of using an ASIC. \$\endgroup\$
    – Joren Vaes
    Jan 18, 2018 at 18:10
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    \$\begingroup\$ An ASIC is hardware. An operating system is software. \$\endgroup\$
    – JRE
    Jan 18, 2018 at 18:25
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    \$\begingroup\$ @DavidLynch I might be wrong, of course or that could be another DavidLynch. But I am pretty sure I saw this name before :) \$\endgroup\$
    – Eugene Sh.
    Jan 18, 2018 at 18:27
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    \$\begingroup\$ If you can describe your application using a Hardware Description Language, then you can have an ASIC made that implements it. \$\endgroup\$ Jan 18, 2018 at 18:29

1 Answer 1


There are so many wrong statements and assumptions that I don't even know where to start.
So let's start with my credentials: I have been designing ASICs for 25 years. I have done small, medium and mega chips. (The latter of course as part of a team).

ASIC chips are hundreds of times faster than traditional chips.

With faster we engineers normally mean the clock speed which is definitely not the case. ASICs run at the same speed as 'normal' chips. After all they are based on the same technology, be it 1.5um or 20 nm (The range with which I have worked).

If we assume hundreds of times faster in functionality. They could be, but only if you can either parallel-up or pipeline the tasks. You would be amazed how often you find that a speed up of five to ten time is the maximum you can achieve. Some algorithms are ideal like a streaming FFT. Others are nasty and require a lot of effort to speed up (h264) (I have heard the new h265 standard is the first time where they starting taking parallel processing into account whilst defining the algorithm.)

Based on what I've read I understand ASIC chips are not very flexible so they cannot be re-programmed.

With that you imply that chips can be reprogrammed. No, they normally can not be reprogrammed. FPGAs and PLDs can but they are not your standard chips. Chips can run programs which is something totally different. As mentioned in the comments: an ASCI/Chip is hardware, a program is software.

Then we get to the core of your question which I would summarise as
How much speed up can I expect if a convert my program into hardware

Nobody can tell.
As I said: it depends on how much of the algorithm can be made to run in parallel or can be pipelined. If you need one end result N and to produce that you need result N-1 you have a problem. If you need a stream of results then ultimately you can instance X cores each working on a result and start them one after the other.

As to cost: I would say a small one is between 500K and 1M. If you need analogue IP (PLL, MIPPI, HDMI, USB, PCIe, SMPS, etc.) your price quickly goes up to 1.5M. Add to that the cost of the ASIC design team.

  • \$\begingroup\$ I like the answer. Nice. I think the OP could use a few additional thoughts, so I may write a supplementary answer (if perhaps one that is from a less well-informed background, as mine is instead as an Intel employee working as a chipset and CPU tester using FPGAs -- plus from my interactions for monster sized x86 simulation boxes built out of FPGAs that Intel used prior to FABing an instance of RTL.) \$\endgroup\$
    – jonk
    Jan 18, 2018 at 19:16
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    \$\begingroup\$ Thanks for your response (instead of down voting a perfectly legitimate question) @jonk I would be very interested in your response too :) Thanks! \$\endgroup\$ Jan 18, 2018 at 19:23
  • \$\begingroup\$ @DavidLynch Unfortunately, the question has been locked and I'm unable to provide what I'd written for you. Life, I guess. \$\endgroup\$
    – jonk
    Jan 19, 2018 at 0:38
  • \$\begingroup\$ A friend from ASIC industry told me that some part of ASIC can be reconfigured these days. Not sure if its true. \$\endgroup\$
    – Mitu Raj
    Jan 19, 2018 at 13:08

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