Newest 'asic' Questions

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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...

asked 2 days ago

Dan Man

11 bronze badge

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votes

1answer

21 views

How to Implement Relational Operation using TCAM?

Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and ...

asic

asked May 26 at 3:10

swr das

31 bronze badge

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2answers

58 views

ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...

digital-logic asic chip-design

asked May 13 at 2:43

ozne

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2answers

106 views

Verilog — The proper way to reset an output signal back to zero on the next clock edge?

Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...

digital-logic fpga verilog synthesis asic

asked May 1 at 0:32

firegurafiku

1996 bronze badges

-1

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2answers

118 views

What ASIC/MCU is in my keyboard?

I disassembled my unbranded USB keyboard to find out what ASIC/encoder/MCU is inside. The chip is (as expected) covered, like the following example: How to find out which chip is underneath?

microcontroller encoder asic keyboard

asked Apr 20 at 19:50

FPU

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3answers

164 views

Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...

integrated-circuit asic chip-design

asked Apr 14 at 19:46

kenny alves

31 bronze badge

3

votes

2answers

141 views

How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...

mosfet vlsi power-consumption asic undervoltage

asked Apr 3 at 1:53

Thorondor

1475 bronze badges

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4answers

141 views

Can an FPGA/ASIC have an Operating System?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes(tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...

fpga cpu computer-architecture asic operating-system

asked Mar 24 at 11:39

Franc M

1134 bronze badges

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0answers

20 views

UCN -1 error in Design Complier synthesis

I have a block for 2's complement in Arithmetic module of a ALU. In the netlist synthesized by Synopsys Design compiler, I find that the 2's complement block output LSB is assigned to input LSB. ie, ...

verilog asic synopsys

asked Mar 22 at 17:29

yk_learner

114 bronze badges

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vote

1answer

64 views

What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?

I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE): ...

digital-logic fpga verilog asic

asked Mar 3 at 3:47

Ralph

619 bronze badges

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0answers

24 views

Can we implement LVDS if my supply voltage is 1.2V?

I am to make output driver for my circuit. In lvds common mode voltage is selected to b3 1.2v. If my supply voltage is 1.2v, is it possible to implement LVDS?

power-electronics asic

asked Feb 21 at 16:15

Syed Adeel Ali Shah

112 bronze badges

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votes

1answer

49 views

Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...

system-verilog vlsi asic

asked Feb 19 at 21:23

shaiko

3691 silver badge8 bronze badges

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0answers

30 views

Do SRAM Macros register the inputs?

In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file). My question is this: SRAMs ...

digital-logic memory sram asic

asked Feb 16 at 0:52

zeke

1332 silver badges10 bronze badges

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vote

2answers

85 views

Does it make sense to use a clock input for combinational logic?

Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter. The requirements were The output should be available in the same cycle The module should ...

digital-logic system-verilog asic rtl

asked Feb 13 at 17:15

Shashank V M

1,7856 silver badges28 bronze badges

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vote

1answer

114 views

How to implement Clock Gating Style RTL into synthesis?

I'm studying to implement a Clock Gating in RTL. So I've followed as the below https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html ...

system-verilog asic soc rtl clock-gating

asked Feb 9 at 14:06

Carter

3254 silver badges18 bronze badges

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vote

2answers

67 views

Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...

vlsi asic chip-design

asked Feb 3 at 12:09

Carter

3254 silver badges18 bronze badges

0

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1answer

89 views

How does the hardware realize adding 8 values in 1 clock cycle? [closed]

For example: result= a1+a2+a3+a4+a5+a6+a7+a8 How many adders are needed to perform this in 1 clock cycle? What does the design look in terms of hardware?

vhdl hardware synthesis asic

asked Dec 24 '20 at 8:19

Vishal bk

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1answer

36 views

Inverter's Chain Sizing

if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ? i know that there are several ...

digital-logic asic

asked Dec 16 '20 at 10:37

Mohamed Sameh

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0answers

65 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...

fpga verilog system-verilog hdl asic

asked Sep 13 '20 at 18:34

arandomuser

18310 bronze badges

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1answer

67 views

How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?

verilog ram asic fifo rtl

asked Aug 21 '20 at 12:34

egeek

1011 bronze badge

0

votes

1answer

172 views

pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...

digital-logic verilog ram sram asic

asked Aug 21 '20 at 5:48

egeek

1011 bronze badge

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vote

3answers

182 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...

fpga xilinx intel-fpga asic actel

asked Aug 6 '20 at 14:09

Electronic_Nerd

1942 silver badges9 bronze badges

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vote

2answers

117 views

Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?

integrated-circuit asic fabrication microfabrication

asked Jul 28 '20 at 15:03

seyyedali hosseini

856 bronze badges

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vote

1answer

52 views

SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...

flipflop system-verilog asic verilator yosys

asked Jul 22 '20 at 15:18

norandomtechie

111 bronze badge

2

votes

4answers

329 views

Hardware to run a fixed neural network

Suppose I have a feedforward neural network and I already have decided what its directed graph, weights and activation function should be. I want a device than runs this neural network as quickly as ...

power hardware asic

asked Jun 28 '20 at 14:04

fdmk40m

294 bronze badges

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0answers

61 views

How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...

vlsi synthesis asic timing-analysis sdc

asked Jun 22 '20 at 6:37

Sai Gautham

1273 silver badges15 bronze badges

0

votes

1answer

46 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...

vlsi synthesis asic cdc sdc

asked Jun 13 '20 at 5:47

zeahr

12 bronze badges

2

votes

2answers

269 views

Meaning of two NOT gates in parallel

Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...

digital-logic schematics asic

asked May 15 '20 at 20:03

Renee Cousins

237 bronze badges

0

votes

1answer

71 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...

integrated-circuit verilog hdl asic

asked May 9 '20 at 7:29

Karthikeya Darivemula

12 bronze badges

0

votes

0answers

20 views

Modelling effects of unbuffered library characterization cell outputs on timing constraint tables

Can someone explain to me or point me to a resource that will shed some light on how (instead of using a buffered library cell, we use a unbuffered library cell) including the effects of unbuffered ...

transistors digital-logic cmos asic timing-analysis

asked Feb 27 '20 at 16:52

j.mar

11 bronze badge

-1

votes

1answer

147 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...

hdl asic

asked Jan 22 '20 at 3:15

0x90

7153 gold badges11 silver badges25 bronze badges

0

votes

1answer

49 views

Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs

I've been looking into some video clock generator chips and almost all of them have a divide-by-2 or CLK/2 output pin (in addition to the normal CLK out). What would be the purpose or application for ...

integrated-circuit signal-processing video rgb asic

asked Dec 2 '19 at 20:46

jparanich

1134 bronze badges

0

votes

1answer

50 views

What is the delay incurred by ternary content-addressable memory (TCAM)?

What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM? I understand their use cases are different. But assume, for an application, I can do an operation using ...

memory asic

asked Nov 7 '19 at 21:30

Rupok Saha

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1answer

58 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...

fpga design system-verilog asic rtl

asked Oct 23 '19 at 7:24

Pramod

548 bronze badges

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vote

0answers

159 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...

power asic modelsim

asked Aug 28 '19 at 18:15

avi1987

111 bronze badge

6

votes

2answers

652 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...

fpga xilinx prototyping asic

asked Aug 8 '19 at 5:43

user3498780

774 bronze badges

1

vote

2answers

268 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...

integrated-circuit asic chip-design

asked Jul 31 '19 at 7:09

seyyedali hosseini

856 bronze badges

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vote

1answer

91 views

Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...

asic

asked Jun 28 '19 at 3:54

Wellnavy

111 bronze badge

0

votes

1answer

846 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...

fpga verilog clock asic jitter

asked Jun 26 '19 at 23:37

user204415

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0

votes

1answer

108 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...

fpga vlsi asic modelsim rtl

asked May 28 '19 at 14:22

Hachani Ahmed

632 bronze badges

0

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0answers

77 views

Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...

flipflop asic metastability

asked Apr 18 '19 at 7:25

njg

1035 bronze badges

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votes

0answers

699 views

Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...

digital-logic asic rtl

asked Mar 25 '19 at 21:13

freezies

12 bronze badges

0

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2answers

594 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...

verilog ram vlsi asic fifo

asked Mar 22 '19 at 15:43

Hachani Ahmed

632 bronze badges

0

votes

1answer

88 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...

fpga verilog xilinx system-verilog asic

asked Mar 4 '19 at 21:37

sxa144

32 bronze badges

0

votes

0answers

57 views

Do Broadcom's Ethernet chipsets need special software to operate?

I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...

ethernet asic network-interface networking

asked Jan 21 '19 at 6:11

M.H

515 bronze badges

2

votes

3answers

561 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...

digital-logic reset asic timing-analysis cdc

asked Jan 13 '19 at 15:01

Prakash Darji

6993 silver badges14 bronze badges

6

votes

1answer

466 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...

synthesis asic rtl

asked Dec 31 '18 at 21:53

oawad

611 bronze badge

1

vote

4answers

767 views

Is an ethernet switch considered as an ASIC?

I work as an electronic reliability engineer. In order to estimate the reliability of integrated circuits, I need to know their type. Thus my question. Is this ethernet switch Marvell Link Street-...

integrated-circuit asic reliability

asked Dec 7 '18 at 9:55

Amine

214 bronze badges

4

votes

5answers

841 views

Are there fully open-source ASICs?

The Ethereum Foundation (an open-source project) will build an open-source ASIC to support its decentralised randomness beacon. To date, has the RTL of any ASIC been open-sourced or will the Ethereum ...

asic open-source open-hardware

asked Oct 26 '18 at 13:06

Randomblue

10.2k26 gold badges92 silver badges170 bronze badges

1

vote

2answers

457 views

Beyond liquid helium cooling

Liquid helium has a boiling point of around -269°C and is used by overclockers. It has led to various world records (e.g. see here and here). What cooling technology can beat liquid helium for the ...

asic cooling

asked Sep 17 '18 at 8:35

Randomblue

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