Newest 'asic' Questions

1 vote

0 answers

64 views

FPGA prototyping vs Formal Verification

FPGAs are used to prototype and test hardware architectures before ASICs are fabricated. Formal verification can also be used to verify the correctness of an RTL architecture or a netlist. Does this ...

learner1

11

asked Jun 27 at 16:19

2 votes

3 answers

108 views

Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...

fpga asic cdc

quantum231

9,669

asked Jun 20 at 1:04

-1 votes

0 answers

41 views

Challenges in implementing super large architectures in latest ASIC (9nm or 12nm or similar)

Recently I came across a few papers that simulate super large accelerator architectures in the latest ASIC, e.g., 9nm or 12nm standard cell libraries. Typically these papers report synthesis results ...

semiconductors asic

learner1

11

asked Jun 15 at 19:17

0 votes

1 answer

35 views

RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?

Given the below scenario, which is a reset-domain-crossing violation : Can it be resolved using some reset synchronization strategy? Is such design considered bad to begin with, i.e. need to avoid ...

digital-logic vlsi asic cdc

Lapid Tech

1

asked May 24 at 4:20

0 votes

1 answer

84 views

ASIC Hardware cost

Why is multiplication with a fixed coefficient cheaper in ASIC as compared to variable multiplication? Would it be faster using an FPGA inferring a DSP Slice?

asic

Rahul Seth

1

asked May 4 at 23:47

1 vote

0 answers

36 views

NEC asic information from around 1990

I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990. More preciselly, any information with specifications of their ASIC/Gate Array lines. I would like to known ...

logic-gates datasheet specifications asic nec

Hernandi F. Krammes F.

121

asked Apr 28 at 2:16

1 vote

1 answer

61 views

8bitworkshop(verilog) to terminal transition

I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...

fpga asic testbench

MatthewRandall

21

asked Jan 7 at 3:49

-1 votes

2 answers

140 views

Is it possible for an SoC to have a built-in SSD?

Is it possible to have an SoC that includes an SSD on-chip, or are there technical constraints that prevent that? What are those technical constraints, if any?

asic solid-state-devices system-on-chip ssd

steventrouble

99

asked Dec 26, 2021 at 3:01

1 vote

2 answers

94 views

Why is static power more of a concern in smaller ASIC geometries than dynamic power?

I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power ...

asic

hontou_

932

asked Nov 17, 2021 at 10:15

5 votes

3 answers

1k views

How is clock gating physically achieved inside an FPGA or ASIC?

It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...

digital-logic fpga asic

quantum231

9,669

asked Nov 15, 2021 at 22:56

3 votes

2 answers

488 views

Does the term micro-architecture have a meaning outside of microprocessors?

Wikipedia defines microarchitecture as follows: In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given ...

digital-logic fpga asic

Quantum0xE7

1,392

asked Oct 11, 2021 at 22:27

10 votes

3 answers

2k views

How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]

One of the applications of FPGAs is to model a computer system/chip/functionality on it prior to mass manufacturing the copies of finalized design. How was this done before FPGAs were used for this ...

fpga asic

lousycoder

381

asked Sep 12, 2021 at 15:22

2 votes

3 answers

681 views

Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?

fpga clock asic cdc

kevin998x

373

asked Sep 7, 2021 at 12:32

0 votes

3 answers

127 views

What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...

fpga asic timing-analysis cdc metastability

Carter

501

asked Sep 5, 2021 at 16:07

-1 votes

1 answer

113 views

Synthesis rules for this procedural assignment (combinational circuit)

I am a noob asking elementary questions. So bear with me. If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...

digital-logic fpga verilog synthesis asic

hardware noob

35

asked Aug 14, 2021 at 2:34

0 votes

1 answer

119 views

Synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me. If I have the following statement in Verilog: ...

digital-logic fpga verilog synthesis asic

hardware noob

35

asked Aug 13, 2021 at 6:37

1 vote

1 answer

142 views

behavior of a pipelined divider

Divider can be made combinational, which uses more logic gates.. Divider can be made sequential, the throughput may stay the same, i.e. use as many stages as the width of the dividend (assuming width ...

verilog hardware asic algorithm divider

hardware noob

35

asked Aug 12, 2021 at 3:08

0 votes

1 answer

92 views

Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...

synthesis asic timing-analysis rtl

Slack

17

asked Jun 29, 2021 at 14:08

0 votes

4 answers

124 views

Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...

fpga flipflop asic timing-analysis cdc

Dan Man

1

asked Jun 9, 2021 at 21:30

0 votes

1 answer

25 views

How to Implement Relational Operation using TCAM?

Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and ...

asic

swr das

3

asked May 26, 2021 at 3:10

0 votes

2 answers

523 views

ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...

digital-logic asic chip-design

ozne

1

asked May 13, 2021 at 2:43

2 votes

2 answers

166 views

What is the proper way to reset an output signal back to zero on the next clock edge?

Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...

digital-logic fpga verilog synthesis asic

firegurafiku

247

asked May 1, 2021 at 0:32

-1 votes

2 answers

347 views

What ASIC/MCU is in my keyboard?

I disassembled my unbranded USB keyboard to find out what ASIC/encoder/MCU is inside. The chip is (as expected) covered, like the following example: How to find out which chip is underneath?

microcontroller encoder asic keyboard

user283482

asked Apr 20, 2021 at 19:50

1 vote

3 answers

783 views

Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...

integrated-circuit asic chip-design

kenny alves

13

asked Apr 14, 2021 at 19:46

3 votes

2 answers

204 views

How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...

mosfet vlsi power-consumption asic undervoltage

Thorondor

147

asked Apr 3, 2021 at 1:53

1 vote

4 answers

996 views

Can an FPGA/ASIC have an operating system?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes (tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...

fpga cpu computer-architecture asic operating-system

Franc M

83

asked Mar 24, 2021 at 11:39

1 vote

1 answer

83 views

What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?

I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE): ...

digital-logic fpga verilog asic

Ralph

81

asked Mar 3, 2021 at 3:47

0 votes

1 answer

128 views

Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...

system-verilog vlsi asic

shaiko

409

asked Feb 19, 2021 at 21:23

0 votes

0 answers

37 views

Do SRAM Macros register the inputs?

In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file). My question is this: SRAMs ...

digital-logic memory sram asic

zeke

143

asked Feb 16, 2021 at 0:52

1 vote

2 answers

247 views

Does it make sense to use a clock input for combinational logic?

Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter. The requirements were The output should be available in the same cycle The module should ...

digital-logic system-verilog asic rtl

Shashank V M

2,411

asked Feb 13, 2021 at 17:15

1 vote

1 answer

1k views

How to implement Clock Gating Style RTL into synthesis?

I'm studying to implement a Clock Gating in RTL. So I've followed as the below https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html ...

system-verilog asic soc rtl clock-gating

Carter

501

asked Feb 9, 2021 at 14:06

1 vote

2 answers

218 views

Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...

vlsi asic chip-design

Carter

501

asked Feb 3, 2021 at 12:09

0 votes

1 answer

92 views

How does the hardware realize adding 8 values in 1 clock cycle? [closed]

For example: result= a1+a2+a3+a4+a5+a6+a7+a8 How many adders are needed to perform this in 1 clock cycle? What does the design look in terms of hardware?

vhdl hardware synthesis asic

Vishal bk

1

asked Dec 24, 2020 at 8:19

-1 votes

1 answer

75 views

Inverter's Chain Sizing

if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ? i know that there are several ...

digital-logic asic

Mohamed Sameh

1

asked Dec 16, 2020 at 10:37

1 vote

0 answers

152 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...

fpga verilog system-verilog hdl asic

arandomuser

193

asked Sep 13, 2020 at 18:34

0 votes

1 answer

122 views

How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?

verilog ram asic fifo rtl

egeek

101

asked Aug 21, 2020 at 12:34

0 votes

1 answer

509 views

Pseudo dual port RAM in verilog

How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo dual port - single port ...

digital-logic verilog ram sram asic

egeek

101

asked Aug 21, 2020 at 5:48

2 votes

3 answers

205 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...

fpga xilinx intel-fpga asic actel

Electronic_Nerd

312

asked Aug 6, 2020 at 14:09

1 vote

2 answers

243 views

Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?

integrated-circuit asic fabrication microfabrication

seyyedali hosseini

85

asked Jul 28, 2020 at 15:03

1 vote

1 answer

75 views

SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...

flipflop system-verilog asic verilator yosys

norandomtechie

11

asked Jul 22, 2020 at 15:18

2 votes

4 answers

355 views

Hardware to run a fixed neural network

Suppose I have a feedforward neural network and I already have decided what its directed graph, weights and activation function should be. I want a device than runs this neural network as quickly as ...

power hardware asic

fdmk40m

29

asked Jun 28, 2020 at 14:04

0 votes

1 answer

76 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...

vlsi synthesis asic cdc sdc

zeahr

1

asked Jun 13, 2020 at 5:47

2 votes

2 answers

459 views

Meaning of two NOT gates in parallel

Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...

digital-logic schematics asic

Renee Cousins

23

asked May 15, 2020 at 20:03

0 votes

1 answer

92 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...

integrated-circuit verilog hdl asic

Karthikeya Darivemula

1

asked May 9, 2020 at 7:29

-1 votes

1 answer

150 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...

hdl asic

0x90

725

asked Jan 22, 2020 at 3:15

0 votes

1 answer

62 views

Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs

I've been looking into some video clock generator chips and almost all of them have a divide-by-2 or CLK/2 output pin (in addition to the normal CLK out). What would be the purpose or application for ...

integrated-circuit signal-processing video rgb asic

jparanich

113

asked Dec 2, 2019 at 20:46

0 votes

1 answer

61 views

What is the delay incurred by ternary content-addressable memory (TCAM)?

What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM? I understand their use cases are different. But assume, for an application, I can do an operation using ...

memory asic

Rupok Saha

1

asked Nov 7, 2019 at 21:30

0 votes

1 answer

68 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...

fpga design system-verilog asic rtl

Pramod

54

asked Oct 23, 2019 at 7:24

1 vote

0 answers

245 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...

power asic modelsim

avi1987

11

asked Aug 28, 2019 at 18:15

6 votes

2 answers

697 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...

fpga xilinx prototyping asic

user3498780

77

asked Aug 8, 2019 at 5:43

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