Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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What does ‘full custom’ really mean?

It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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What/why are the patterns in the "unused" portion of this ASIC?

The below image is a 150um x 170um block from an ASIC design file produced automatically by fully open-source tools such as yosys. The apparently unused sections have a repetitive pattern, presumably ...
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How to do clock signal rising edge detection in Chisel (scala)?

I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote. ...
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Is it possible to reset SRAM in one cycle?

If you have some SRAM in an ASIC and you want to reset it to 0 quickly, rather than looping over the entire memory can you just write to all words in parallel by asserting all word lines at once (this ...
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Can we say that a CPU is an ASIC that is designed to perform a wide range of instructions?

My question is more terminological than technical. I have come across different definitions of what an ASIC is. The most common one is that an ASIC is an IC that is designed for a specific application ...
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Can a digital system be considered an ASIC regardless its physical implementation?

From my knowledge from classical books of computational and digital systems, an ASIC is a category of full-customized or semi-customized integrated circuit (IC) tailored to a specific application. ...
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Are SR latches bad in ASIC design?

I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
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How does the switch in this board control four different states in the LED? [closed]

I have the simplest board with a LED and a switch, powered by 2 CR2032 3V (pictures attached). There is 4 possible states: LED is off. LED flashing slowly. LED flashing fast. LED is constantly on. ...
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Clock domain crossing without synchronisers

I am (re)designing an SPI slave module in VHDL for an ASIC. The SPI domain is faster than the main clock domain (~10MHz and ~1MHz), so the SPI state machine operates in the SPI domain. The previous ...
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Reconciling phase shift error of length-tuned structures in 81-86GHz I/Q direct down-converter ASIC with datasheet specifications

I'm watching a video on reverse engineering a GaAs 81-86GHz I/Q down-converter ASIC. The relevant section of the video for this question is 10 minutes onwards, but watching the video isn't necessary ...
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What is name of the technique where we create modules to help us test our digital design?

In my FPGA design project, I created a few modules that can be used to emulate output from another module. Then there were modules that would inject erronous data or signals that signify errors. By ...
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Pin vs Port terminology in SDC

In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
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Standard cell design flow in an ASIC design flow

I have a question regarding the standard cell design flow in an ASIC design flow. That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
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What are horizontal and vertical track pitches?

I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
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Why don't 2 flip-flop synchronizers have a reset?

This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily". So, my question is: Why do almost all of ...
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Why is a reset with asynchronous assert safe?

As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
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Does an ASIC have an instruction set? [closed]

Does an Application Specific Integrated Circuit have an instruction set like a CPU? If yes, then that would contradict the statement "ASIC is faster than CPU" because having an instruction ...
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Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...
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RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?

Given the below scenario, which is a reset-domain-crossing violation : Can it be resolved using some reset synchronization strategy? Is such design considered bad to begin with, i.e. need to avoid ...
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ASIC Hardware cost

Why is multiplication with a fixed coefficient cheaper in ASIC as compared to variable multiplication? Would it be faster using an FPGA inferring a DSP Slice?
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NEC asic information from around 1990

I'm looking for datasheets with specification for the NEC ASIC/Gate Arrays from around 1990. More preciselly, any information with specifications of their ASIC/Gate Array lines. I would like to known ...
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8bitworkshop(verilog) to terminal transition

I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
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Is it possible for an SoC to have a built-in SSD?

Is it possible to have an SoC that includes an SSD on-chip, or are there technical constraints that prevent that? What are those technical constraints, if any?
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Why is static power more of a concern in smaller ASIC geometries than dynamic power?

I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power ...
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How is clock gating physically achieved inside an FPGA or ASIC?

It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
quantum231's user avatar
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Does the term micro-architecture have a meaning outside of microprocessors?

Wikipedia defines microarchitecture as follows: In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given ...
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How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]

One of the applications of FPGAs is to model a computer system/chip/functionality on it prior to mass manufacturing the copies of finalized design. How was this done before FPGAs were used for this ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...
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Synthesis rules for this procedural assignment (combinational circuit)

I am a noob asking elementary questions. So bear with me. If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
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Synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me. If I have the following statement in Verilog: ...
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behavior of a pipelined divider

Divider can be made combinational, which uses more logic gates.. Divider can be made sequential, the throughput may stay the same, i.e. use as many stages as the width of the dividend (assuming width ...
hardware noob's user avatar
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How to Implement Relational Operation using TCAM?

Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and ...
swr das's user avatar
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ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...
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What is the proper way to reset an output signal back to zero on the next clock edge?

Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
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What ASIC/MCU is in my keyboard?

I disassembled my unbranded USB keyboard to find out what ASIC/encoder/MCU is inside. The chip is (as expected) covered, like the following example: How to find out which chip is underneath?
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Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
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How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...
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Can an FPGA/ASIC have an operating system?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes (tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
Franc's user avatar
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What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?

I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE): ...
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Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...
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Do SRAM Macros register the inputs?

In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file). My question is this: SRAMs ...
zeke's user avatar
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Does it make sense to use a clock input for combinational logic?

Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter. The requirements were The output should be available in the same cycle The module should ...
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How to implement Clock Gating Style RTL into synthesis?

I'm studying to implement a Clock Gating in RTL. So I've followed as the below https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html ...
Carter's user avatar
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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How does the hardware realize adding 8 values in 1 clock cycle? [closed]

For example: result= a1+a2+a3+a4+a5+a6+a7+a8 How many adders are needed to perform this in 1 clock cycle? What does the design look in terms of hardware?
Vishal bk's user avatar
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Inverter's Chain Sizing

if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ? i know that there are several ...
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SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
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