Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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8bitworkshop(verilog) to terminal transition

I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
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Is it possible for an SoC to have a built-in SSD?

Is it possible to have an SoC that includes an SSD on-chip, or are there technical constraints that prevent that? What are those technical constraints, if any?
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Why is static power more of a concern in smaller ASIC geometries than dynamic power?

I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power ...
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How is clock gating physically achieved inside an FPGA or ASIC?

It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
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Does the term micro-architecture have a meaning outside of microprocessors?

Wikipedia defines microarchitecture as follows: In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given ...
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How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]

One of the applications of FPGAs is to model a computer system/chip/functionality on it prior to mass manufacturing the copies of finalized design. How was this done before FPGAs were used for this ...
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
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What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...
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Synthesis rules for this procedural assignment (combinational circuit)

I am a noob asking elementary questions. So bear with me. If I have the following code, what would the synthesis result be if it can be synthesized at all. will the synthesizer generate intermediate ...
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Synthesis output for the following verilog code

I have a somewhat stupid question as I am still a noob. So bear with me. If I have the following statement in Verilog: ...
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77 views

behavior of a pipelined divider

Divider can be made combinational, which uses more logic gates.. Divider can be made sequential, the throughput may stay the same, i.e. use as many stages as the width of the dividend (assuming width ...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How to Implement Relational Operation using TCAM?

Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and ...
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ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...
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What is the proper way to reset an output signal back to zero on the next clock edge?

Occasionally writing some FPGA-targeted Verilog code at my job, I often need to drive output signals high during one clock cycle exactly. Sometimes I use the following “trick“ to achieve this (let me ...
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What ASIC/MCU is in my keyboard?

I disassembled my unbranded USB keyboard to find out what ASIC/encoder/MCU is inside. The chip is (as expected) covered, like the following example: How to find out which chip is underneath?
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Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
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How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...
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488 views

Can an FPGA/ASIC have an Operating System?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes(tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
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What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?

I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE): ...
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Can we implement LVDS if my supply voltage is 1.2V?

I am to make output driver for my circuit. In lvds common mode voltage is selected to b3 1.2v. If my supply voltage is 1.2v, is it possible to implement LVDS?
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Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...
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Do SRAM Macros register the inputs?

In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file). My question is this: SRAMs ...
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Does it make sense to use a clock input for combinational logic?

Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter. The requirements were The output should be available in the same cycle The module should ...
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254 views

How to implement Clock Gating Style RTL into synthesis?

I'm studying to implement a Clock Gating in RTL. So I've followed as the below https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html ...
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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How does the hardware realize adding 8 values in 1 clock cycle? [closed]

For example: result= a1+a2+a3+a4+a5+a6+a7+a8 How many adders are needed to perform this in 1 clock cycle? What does the design look in terms of hardware?
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Inverter's Chain Sizing

if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ? i know that there are several ...
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SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
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How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
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Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?
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SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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Hardware to run a fixed neural network

Suppose I have a feedforward neural network and I already have decided what its directed graph, weights and activation function should be. I want a device than runs this neural network as quickly as ...
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SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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Meaning of two NOT gates in parallel

Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...
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81 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...
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Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs

I've been looking into some video clock generator chips and almost all of them have a divide-by-2 or CLK/2 output pin (in addition to the normal CLK out). What would be the purpose or application for ...
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What is the delay incurred by ternary content-addressable memory (TCAM)?

What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM? I understand their use cases are different. But assume, for an application, I can do an operation using ...
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FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
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283 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
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Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...
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Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...