Electrical Engineering

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An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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How does the hardware realize adding 8 values in 1 clock cycle? [closed]

For example: result= a1+a2+a3+a4+a5+a6+a7+a8 How many adders are needed to perform this in 1 clock cycle? What does the design look in terms of hardware?
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Inverter's Chain Sizing

if i have a chain of 4 identical inverters connected in series and i want to size them to obtain a specific propagation delay time, how do I approach this problem ? i know that there are several ...
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SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
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1answer
54 views

How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
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174 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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2answers
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Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?
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1answer
42 views

SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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4answers
322 views

Hardware to run a fixed neural network

Suppose I have a feedforward neural network and I already have decided what its directed graph, weights and activation function should be. I want a device than runs this neural network as quickly as ...
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How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...
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42 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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224 views

Can FPGAs be emulated on a CPU?

Can FPGAs be emulated on general purpose computers? As per Church-Turing thesis all Turing machines can be emulated on the universal Turing machine. So if the FPGA can emulate processors, can the ...
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200 views

Meaning of two NOT gates in parallel

Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...
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67 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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49 views

Get net names from LEF files

I'm analyzing the layout of a circuit by parsing the LEF and DEF files with PyParsing (Python). I parsed everything, no problem in this part. I also have on the side the netlist of the circuit. My ...
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UPF for low power design

I want to write simple UPF for doing power supply connection for the design. I have top level design (eg name TOP) having 6 different power supplies.I am not sure while defining domain how to use '...
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Modelling effects of unbuffered library characterization cell outputs on timing constraint tables

Can someone explain to me or point me to a resource that will shed some light on how (instead of using a buffered library cell, we use a unbuffered library cell) including the effects of unbuffered ...
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146 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...
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Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs

I've been looking into some video clock generator chips and almost all of them have a divide-by-2 or CLK/2 output pin (in addition to the normal CLK out). What would be the purpose or application for ...
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46 views

What is the delay incurred by ternary content-addressable memory (TCAM)?

What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM? I understand their use cases are different. But assume, for an application, I can do an operation using ...
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54 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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106 views

Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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602 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
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258 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
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Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...
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1answer
584 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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86 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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70 views

Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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368 views

Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...
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468 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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80 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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53 views

Do Broadcom's Ethernet chipsets need special software to operate?

I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...
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3answers
467 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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416 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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4answers
683 views

Is an ethernet switch considered as an ASIC?

I work as an electronic reliability engineer. In order to estimate the reliability of integrated circuits, I need to know their type. Thus my question. Is this ethernet switch Marvell Link Street-...
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5answers
683 views

Are there fully open-source ASICs?

The Ethereum Foundation (an open-source project) will build an open-source ASIC to support its decentralised randomness beacon. To date, has the RTL of any ASIC been open-sourced or will the Ethereum ...
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377 views

Beyond liquid helium cooling

Liquid helium has a boiling point of around -269°C and is used by overclockers. It has led to various world records (e.g. see here and here). What cooling technology can beat liquid helium for the ...
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49 views

Maximum power draw density of digital ASIC

Given a process node (e.g. TSMC's 16nm FinFET+) what is the maximum power per mm2 that a digital ASIC can draw? Secondary question: Assuming liquid nitrogen cooling, what would be the bottleneck ...
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How can I access process node data sheets?

I am searching for process node data sheets. Specifically, I'm interested in TSMC's 16nm, 12nm, 10nm, 7nm nodes, as well as Samsung's 14nm, 10nm nodes. I did not find anything with Google. How can I ...
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228 views

Gate and routing delays as a function of voltage and temperature

As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating ...
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439 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
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What is meant by process “performance”?

I am reading the product page for TSMC's 20nm process. It states Compared to its 28nm node, the 20nm process provides 15% better performance and can reduce total power consumption by a third. What ...
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1answer
199 views

Large SiGe ASICs for digital logic

I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a ...
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113 views

65nm silicon-germanium

The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process. ...
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678 views

Exotic semiconductors for fast digital ASIC

I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
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783 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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69 views

How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
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Gated integrator IC, non continuous

Can anyone give me any suggestions for some good gated voltage integrators that aren't continuous, and more like a boxcar integrator? I want to integrate the the total voltage across a pulse coming ...
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521 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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572 views

What material(s) are used in IC's as insulating layers between metal layers?

This question and the answers hits close to the topic. One picture shows it as SOD. Silicon-oxide dielectric? I'm aware that around/within the transistor, silicon oxide is grown for insulation where ...

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