Is it Possible to Design an Entire Operating System or App using ASIC Chips? [closed]

Question

ASIC chips are hundreds of times faster than traditional chips.

Is it possible to design an entire operating system or application using a full custom ASIC chip?

Based on what I've read I understand ASIC chips are not very flexible so they cannot be re-programmed but what if I do not plan on changing my program in the future and just want to take advantage of the speed increase ASIC offers - is something like this possible or is it limited to relatively simple functionality such as hash functions?

If something like this is possible I have two more questions:

• What magnitude of speed increase can I expect over traditional CPUs?
• What could I expect to spend on such a device (I know it could cost about $1 million to design one such chip)

Thanks

Edit:

I think there's a lot of confusion surrounding this question but basically I am trying to understand the limitations of ASIC chips. My understanding is that the only limitation of ASIC chips is that the algorithm (or whatever "software") they run is fixed and cannot be changed (somehow the chips are designed to execute a specific algorithm). So if I had an application which is fixed in nature could the application benefit from ASIC technology?

@JRE "An ASIC is hardware. An operating system is software" - how did I imply otherwise?

Answer 1

There are so many wrong statements and assumptions that I don't even know where to start.
So let's start with my credentials: I have been designing ASICs for 25 years. I have done small, medium and mega chips. (The latter of course as part of a team).

ASIC chips are hundreds of times faster than traditional chips.

With faster we engineers normally mean the clock speed which is definitely not the case. ASICs run at the same speed as 'normal' chips. After all they are based on the same technology, be it 1.5um or 20 nm (The range with which I have worked).

If we assume hundreds of times faster in functionality. They could be, but only if you can either parallel-up or pipeline the tasks. You would be amazed how often you find that a speed up of five to ten time is the maximum you can achieve. Some algorithms are ideal like a streaming FFT. Others are nasty and require a lot of effort to speed up (h264) (I have heard the new h265 standard is the first time where they starting taking parallel processing into account whilst defining the algorithm.)

Based on what I've read I understand ASIC chips are not very flexible so they cannot be re-programmed.

With that you imply that chips can be reprogrammed. No, they normally can not be reprogrammed. FPGAs and PLDs can but they are not your standard chips. Chips can run programs which is something totally different. As mentioned in the comments: an ASCI/Chip is hardware, a program is software.

Then we get to the core of your question which I would summarise as
How much speed up can I expect if a convert my program into hardware

Nobody can tell.
As I said: it depends on how much of the algorithm can be made to run in parallel or can be pipelined. If you need one end result N and to produce that you need result N-1 you have a problem. If you need a stream of results then ultimately you can instance X cores each working on a result and start them one after the other.

As to cost: I would say a small one is between 500K and 1M. If you need analogue IP (PLL, MIPPI, HDMI, USB, PCIe, SMPS, etc.) your price quickly goes up to 1.5M. Add to that the cost of the ASIC design team.