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When I search for level shifting 5V pulse to 12V, I came to know about the circuit given below. enter image description here

It is simply based on a push-pull amplifier configuration as you all know. And what I have understood is, when the input reaches 5V (high) level, then Q1 conducts and since it is an NPN transistor, it will make the gate of the MOSFETs both low so that Q3 starts to conduct and vice versa for when an input is 0V. When we see a graph in an oscilloscope it will show 12V pulse as in the attached graph given below.

But when input pulse goes low (0V), I cannot see an output voltage at 0V. Instead, I am getting 6.366V in output wave instead of 0V. why does that happen and how to resolve this problem?

enter image description here

Thanks for the help in advance!

Edit: As per suggestions from the comment, I have attached an output node.

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  • \$\begingroup\$ 1. Which node is the output? 2. Was Q3 upside down like it is in your schematic when you did the simulation? \$\endgroup\$
    – The Photon
    Commented Apr 5, 2018 at 4:14
  • \$\begingroup\$ Notice the body diode drawn in the Q3 symbol. With that diode in mind, how much current would have to go through the Q2 drain to drive the output low? \$\endgroup\$
    – The Photon
    Commented Apr 5, 2018 at 4:16
  • \$\begingroup\$ Just curious. Do you want a push-pull driver? If so, what slew rates and what current compliances? How fast and what kind of load must it drive? \$\endgroup\$
    – jonk
    Commented Apr 5, 2018 at 4:26
  • \$\begingroup\$ @jonk, I just thought and got curious about how to level shift 5V to 12V when I meet that situation. That's all. \$\endgroup\$
    – CNA
    Commented Apr 5, 2018 at 4:31
  • \$\begingroup\$ @ThePhoton, Yes. Q3 was like that when I did a simulation and the output node is shown now. \$\endgroup\$
    – CNA
    Commented Apr 5, 2018 at 4:35

1 Answer 1

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The most apparent serious problem with the circuit is that you have the Source and Drain of this FET wrong way around in the circuit. Note how the body diode will conduct a lot of current when the lower FET tries to pull low.

enter image description here

If you want a chance of getting a 5V to 12V driver circuit working prepare it more like this configuration and get rid of a couple of transistors in the process.

enter image description here

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  • \$\begingroup\$ If so, as said in your answer, If I change the mosfet, will it solve a problem? \$\endgroup\$
    – CNA
    Commented Apr 5, 2018 at 4:33
  • \$\begingroup\$ @Dhans - Yeah it probably would work but as I've shown in my answer there really is no need for the intermediate BJT pair. \$\endgroup\$
    – Michael Karas
    Commented Apr 5, 2018 at 14:31
  • \$\begingroup\$ Yes. I have tested it and then only I accepted your answer. \$\endgroup\$
    – CNA
    Commented Apr 5, 2018 at 16:47
  • \$\begingroup\$ Note that the stacked output FETS may see some shoot through current right at the time of switching at the gates. If this is too much you may \$\endgroup\$
    – Michael Karas
    Commented Apr 5, 2018 at 18:19
  • \$\begingroup\$ ...may want to put a small resistor in series with the V+ supply above the upper FET in the stack. \$\endgroup\$
    – Michael Karas
    Commented Apr 7, 2018 at 8:53

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