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I have ask this question in here before:Simulation is the same as my thinking,but different from the pape r(charging loop) ,and @a concerned citizen showed his\her simulation and schematic to me.However,everything,except the diode and switch,is the same as his ,but our simulation are different.By the way,his simulation is right,that is,the same as paper.

Our simulation are different,here are our difference:

1.His positive half wave or negative half wave start from a positive or negative voltage,but mine start from 0V.

enter image description here

His schematic information and simulation

2.At the 0ms,his voltage is about 1.4V,and at this moment,all switch is opened,that is ,the equivelent circuit should be like this.And i think that is very strange,because at 0ms,the sine current source just ready to produce sine wave,and the capacitor,which initial condition is 2V ,did't connect that C1 with their positive pin ,why is there a 1.4V in the 0ms?

schematic

simulate this circuit – Schematic created using CircuitLab

@a concerned citizen told me that You're probably using something similar to uic (initial conditions), I let the solver determine the .op. If I had used with uic, it would have, most likely, started from zero (everything).However,the simulation still start from 0V when i don't use the UIC.What is this mean by using .op?does anyone know that?

enter image description here

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    \$\begingroup\$ it seems that your question has been answered previously ..... everything,except the diode and switch,is the same ... not true, you are also using different software from @aconcernedcitizen \$\endgroup\$
    – jsotola
    Commented Apr 27, 2018 at 6:46
  • \$\begingroup\$ but shouldn't the simulation be similar?Because @aconcernedcitizen simulation is symmetry predamp,but mine is no-predamp.I know different software simulation should't be the same,but they be similar. \$\endgroup\$
    – XM551
    Commented Apr 27, 2018 at 6:55

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The solver in LTspice, unless special conditions apply, tries to calculate the operation point (OP) of the circuit prior to simulation, because the circuit is considered to have been running since the Big Bang and the simulation's t=0 means the start is somewhere down the road, which also means that the circuit had time to reach an OP, and that's what the solver tries to find.

If uic is explicitly set, that's a flag telling the solver that t=0 coincides with the creation of the Universe itself, and everything starts from zero. Note that this is different thatn specifying ic=X on a cap, for example, where that means the OP will still be calculated by the solver, but with a special, particular initial condition (IC) on that particular cap, only (or on any other element that uses ic). Setting uic disables any other particular ic.

I don't know how Cadence solves it, or if it has some additional setting, somewhere else, about solving for the op, but here's how LTspice shows the waveform when uic is set:

sim

As you can see, it's nothing special, it just starts from zero and, eventually, it reaches the steady-state as seen in the previous answer.

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