I've been asking similar question which received some downvotes, so I'm reformulating my task (hopes this one gives more clarity).
I'm planning to establish a high-speed (3 Gpbs full duplex) serial connection between two fpga boards (distance between the chips < 15 cm, including the connectors), more precisely between spartan 6 and artix 7 devices (these are not absolute requirements, but appear to be the cheapest ones having integrated transceivers inside).
I'm not sure about what protocol should I pick. I've been digging into RapidIO specs lately, but it looks like I have to use a switch chip to connect devices, but switches are pretty expensive (~ $150/piece) and introduce at least 100 ns delay, as well as 10+ layers PCB requirement (example).
PCIExpress is not an option (though connector is nice), since it introduces around 500ns delay, and ideally I'm looking into sub 100ns transmit latency (from parallel stream inside one fpga to parallel stream inside another). Due to high latency 10Gb Ethernet is also not an option.
There's also an Aurora protocol from Xilinx (link), but I cannot find any PHY layer definitions and delay numbers. More of that, despite all high-speed serdes applications advertise low pin counts, all dev boards with embedded transceivers use either SMC, optical or cryptic mezzanine card connectors with 400 pins. Is there any other option? Like, ~50 pin connector or less. So, to sum this up, questions are:
- Is it possible to achive sub 100ns delay between two chips using serdes?
- Are there any PHY specs/examples for Aurora?
- Will it be simpler to throw wide BLVDS interface and use high-clock parallel bus?
Any suggestion is greatly appreciated!