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I have the following setup to control 256 bi-polar stepper motors from a data stream via SPI.

I'm deciding between an MCU (teensy 3.6) or an FPGA.

Each motor (four wire) is driven by a driver that requires 2 GPIO's (A4988).

I use 32 16-bit shift registers to talk to the 256 drivers from around 36 GPIOs on the MCU/FPGA.

I want each motor to respond in unison when i issue commands, essentially they should be controlled in Parallel. An FPGA should do this well, but coding on one is not so trivial.

Using a Teensy 3.6 for the MCU approach, i would like to know how 'parallel' the control would be.

I.E. I have 32 Data lines going from 32 GPIOs to 32 16-bit Shift registers; I want to turn all steppers fully on in the same direction: how long is the latency between the command being output from GPIO 1 to GPIO 32?

Here is a block diagram to aid the setup.

enter image description here

I would probably go with the MCU approach if the latency is negligible, but i would like to know your thoughts. I would imagine any latency only being an issue since i bridge all other shift register control pins (latch, clock etc).

Thanks

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    \$\begingroup\$ GPIO latency is secondary comparing to the SPI communication \$\endgroup\$ – P__J__ Jun 1 '18 at 14:03
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    \$\begingroup\$ If you use a shift register such as a 74HC595, all the outputs can be made to change simultaneously (within nanoseconds) by feeding RCLK to all in parallel. \$\endgroup\$ – Spehro Pefhany Jun 1 '18 at 14:10
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    \$\begingroup\$ You probably do not want step pulse generation downstream of a serial shift register, SPI or otherwise. High end MCUs like on your board are available in high pin count versions. If you've not worked with FPGAs before, beware there is a huge learning curve there. \$\endgroup\$ – Chris Stratton Jun 1 '18 at 14:39
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    \$\begingroup\$ It isn't clear why you are concerned with individual GPIO latency, unless you have a library that can control only individual GPIO bits. It looks like you want to make a 512-bit parallel register, and toggle all bits simultaneously. This can be achieved, as Spehro said, with parallel clock/output control. But you will need also to load all 32x16 registers from the same MCU pipe, which will take 32 writes, 32 latch toggling, 32 clock toggling, etc, which will also take software time. So the initial MCU parallel output difference might be not your main concern. \$\endgroup\$ – Ale..chenski Jun 1 '18 at 18:23
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Depends on how you wire up the shift registers. Usually shift registers will have three input pins: data, clock, and latch. Rising edge on clock will shift in/through a data bit, rising edge on latch will transfer the contents of the internal serial registers to the parallel output registers. So if you tie all of the latch pins together and drive them at the same time, all of the shift register outputs will update at nominally the same time (within a few ns). If you want the least skew between the outputs, this is the way to do it.

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Lets assume you have an MCU with two 32-bit ports. Next you take fourteen SN74ALVCH16721 20-bit D-registers. (Just to have some spare bits!) To write to one you could:
- Set the data on port1
- write the clock high on port2
- Write the clock low on port2

For fourteen chips that is 42 writes. With a 64MHz CPU that takes ~218 nsec. Lets add a fudge factor of ten because the instruction must be fetched: ~2uSec. You think your motors will notice?

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  • \$\begingroup\$ The Op is using a Teensy, but does not specify which one, so it could be anything from 16Mhz (AVR) through 180Mhz (Cortex M4F). That makes a lot of difference. Whether the motors would notice is not the question. \$\endgroup\$ – Jack Creasey Jun 1 '18 at 22:18
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GPIOs in MCUs are usually organized as registers of certain width, typically matching the internal MCU architecture. If you attach some of your I/Os to the same register, say 8-bit register, you can have all these GPIOs to change nearly simultaneously, the difference will be in sub-nanosecond time frame (plus possible tracing length mismatch). But if you have a wider bus and your GPIOs are split between different MCU registers, then there will be delay between the groups, few MCU clock cycles, depending how your software handles individual register read-writes.

Regarding FPGA, driving wide parallel busses has a known problem of power starvation due to limited internal ability of FPGA to deliver current to GPIOs. Specifications for FPGA usually have very specific restrictions on how many GPIOs can be switched simultaneously, you need to consult with datasheets before planning the FPGA design.

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