reverse engineering the Nord Lead 4 control board

Question

I am reverse engineering a synthesizer named nord lead 4. I want to tap in between the control board and mainboard which has the microprocessor.

i didn’t started with the powered on analysis but i am making a map of the connections and getting to know the IC’s.

I figured out all the pins of the 26 pin cable between the control board(which has potentiometers and two leg switches and 7 segment led displays etc.).

This board has also the IC’s that i am interested 3 ADC ‘s (max1039) a mux/demux(hc4052) 2 octal bus trancievers(lc245a) and probably for the seven segmented displays 6 flipflop IC’s(hct374) and one demux(lvc138a).

I also figured out all the selects and connection between the ADC’s and the mux/demux hc4052. This is mostly all i understand from topology until now.

My question is about the switches. There are around 34 switches in this control board(the ones you press with your finger they are momentary switches) they have two legs when you press there is a connection created between the two legs ofcourse.

These switctches are distributed to 8 busses of the octal tranciever(lc245a) and those busses sent to the other board which has the microprocessor. So multiple switches are on the same bus. Do you have an idea how this machine reads them and know which is which? Does this topology seem familiar to you?

Thank you very much Please tell me if you need more info.

*i hope i put the right tags to the question

Answer 1

You can identify and match functions to pins. Only the OEM designer knows how they are read into memory. Usually by a chip select to enable bus side read. From ‘138

8 switches need 3 bits to address.
32 switches need 5 bits to address.
38 switches need 6 bits to address. Or 8 bits as done here.

This can be done with 3 bits to ‘138 and 3 more bits from CPU using matrix array if switches are not grounded. This uses typical low to select 1 of 8 rows and “1” to bias 5 Columns with diodes or in software input open cct or output=1. Thus 3+5 software switches = 8 bits from CPU during port 8 address bits then read switches like RAM. Or any variation of this.

CPU inputs 3 but address to ‘138 decoder to select 1 of 8 latches in a sequential manner as fast as it needs to. Classic bus MUX.