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This video succinctly describes why the read/modify/store has potential problems when it comes to interrupts. Very clear and understandable.

He uses the TI Stelarris Cortex-M4 as a teaching board and in the minute I linked above describes how that board was designed such that one can write to each GPIO bit or a group of bits as it were a single address using 256 different 32-bit registers.

I am following along with a blue-pill STM32F103C8T6 board and page 150 of the reference manual says:

Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. G).

Dave Welche's code does exactly this. It works exactly as expected and blinks the onboard LED.

My question then: Is there a way to do atomic writes to the blue-pill board in the way that's described in the video? Or is that each manufacturer handles this type of thing differently and in the case of the blue-pill ST has decided to use a single register to handle this?

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GPIO design is nominally unique to each ARM licensee, and potentially can differ between a vendor's different sub-families.

However, most ARM MCUs are setup to put the GPIO in the bit-banding region, which aliases each individual bit to its own distinct address - a feature provided by the ARM design, rather than the vendor.

The Stellaris parts in question however have a novel capability that appears to be an aspect of their GPIO design, rather than an ARM bit-banding:

To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 662) by using bits [9:2] of the address bus as a mask. In this manner, software drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins. This method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this feature, the GPIODATA register covers 256 locations in the memory map.

The implication here is that you can mask off any combination of 8 bits in one of this chips relatively large number of relatively small 8-bit ports.

In contrast, the STM32 BSRR/BRR is another vendor-unique scheme. Note that because the BSRR register has distinct bits for each of set and reset, it is also possible to do a masked operation on an arbitrary combination of bits of a wider 16-bit GPIO register here. However, the data would have to be pre-processed to split the sets from the resets (vs. the TI solution which is a masked binary write) and reading would appear to require post-masking by software.

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  • \$\begingroup\$ Thanks Chris! I think I get it. Quick follow up, you said each individual bit having a unique address is an ARM design, so how could I compose an address for GPIO PC13? Which register + offset would I be using? Secondly I get your point about the BSRR, one would have to compose some mask that turns on a group of pins together in one of the 16 positions at once, rather than a unique address for a group. Still would be nice to know how to compose the address for a single pin. \$\endgroup\$ – Sam Hammamy Aug 27 '18 at 18:55
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    \$\begingroup\$ @SamHammamy that is a new question and not in the scope of comments. \$\endgroup\$ – Arsenal Aug 27 '18 at 20:29
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    \$\begingroup\$ @SamHammamy - you should look at the ARM bit-banding docs and get the base address of the data register from the STM32 programmer's manual \$\endgroup\$ – Chris Stratton Aug 27 '18 at 21:02
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    \$\begingroup\$ I cant remember if bit banding is an option that the vendor can choose to support or not and if so if all the cortex-ms have it. Chris hit the nail squarely on the head on this one the core might help the vendor does vendor stuff. And to see if the core helps then start with the arm docs. Now that I think about though I know the blue pill has bit banding regions because I found that in some code one was there, and it wasnt in the st documentation. \$\endgroup\$ – old_timer Aug 27 '18 at 21:40
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    \$\begingroup\$ the vendor is involved in that the base address of the region is to some extent controlled by the chip vendor and then works as arm documents on top of that offset/address. \$\endgroup\$ – old_timer Aug 27 '18 at 21:40

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