1
\$\begingroup\$

I'm trying to find the conversion time of ADC of this (page 1083) microcontroller. The first thing I see is 1 MHz conversion rate in "42.2 Embedded Characteristics" (page 1084).

Also, in "42.6.1 Analog-to-Digital Conversion" is mentioned "ADC conversions are sequenced by two operating times: the tracking time and the conversion time." It's easy to find the tracking time but I'm a little confused by the second part "conversion time".

In page 1173, "Table 44-41. ADC Timing Characteristics" I see "tCONV" 20 (typ) tcp_adc (clock periods). enter image description here I reckon the clock period is that it's mentioned in the second row of the table which is from 45ns to 1000ns. Those numbers give exactly the frequency numbers as the first row.

The most confusing part for me is in page 1089 (42.6.2 ADC Clock). enter image description here This section says that the frequency is between Fperiph_clk/2 (60 MHz) and Fperiph_clk/512 (234.375 KHz). According to the datasheet the Fperiph_clk is the master clock which is 120 MHz. These values are much different than the values of the table above.

Am I missing something here?

\$\endgroup\$
1
\$\begingroup\$

The quoted section also says: "PRESCAL must be programmed to provide the ADC clock frequency parameter given in the section "Electrical Characteristics"

What is unclear here? You have whatever the system frequency is, then PRESCAL it to meet the ~20-22 MHz fADC. Then you will have the total best sampling time as a sum of tracking time and conversion time (20 ADC clocks), or something along these lines.

CORRECTION: the tracking time is included in conversion time, according to Note3:

enter image description here

It takes 5 clocks for HOLD, and minimum 15 for conversion/tracking. It is true that the specs are alittle bit vague on terminology.

\$\endgroup\$
3
  • \$\begingroup\$ what would happen if the Fperipheral_clk / PRESCAL is outside of the range of electrical characteristics? \$\endgroup\$
    – MrBit
    Mar 14 '19 at 17:04
  • \$\begingroup\$ You would loose accuracy. With a clock too low the S&H capacitor might discharge and with a clock too high the conversion has not enough time to settle, because transition times of the logic unit might need longer. \$\endgroup\$
    – jusaca
    Mar 14 '19 at 17:08
  • \$\begingroup\$ @MrBit, I would guess that if the tADC is too small (frequency above 22 MHz, the ADC won't work correctly, skip values, or something. And loose accuracy on fast-changing signals, as jusaca noted. \$\endgroup\$ Mar 14 '19 at 17:08
0
\$\begingroup\$

So, you have a little bit of tolerance, when you use another master clock, you are not forced to run the chip with 120 MHz.

Just set the prescaler to a value, so that you stay inside the recommended ADC clock window.

\$\endgroup\$
2
  • \$\begingroup\$ what do you mean a little bit of tolerance? \$\endgroup\$
    – MrBit
    Mar 14 '19 at 16:58
  • \$\begingroup\$ OK, tolerance might be the wrong term here. I meant to say, that you have the possiblity to adjust the ADC clock to lower or higher frequencies, for when you have a clock different from 120 MHz. The large prescaler range gives you more freedom in choosing the right clock ;) \$\endgroup\$
    – jusaca
    Mar 14 '19 at 17:06

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.