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I have disassembled a "Chinese" power inverter, I found a High-Frequency Transformer, with no label on it.

I would like to make an inverter using this transformer to generate the High voltage to feed into a full bridge to make a pure/modified sine wave inverter. I "I reversed engineered" the inverter, I found that the transformer was driven in the following way(using center tapped transformer instead of a full bridge):

Simple schematics of original inverter

The question is, how I can calculate the best/optimal switching frequency for this HF transformer, assuming I can measure its resistance and inductance?

I need to know where the core saturates and then apply the reverse of V=4.44*N1*f*Bmax?

How the switching frequency will impact the performance(voltage ripple, idle current, losses)?

How PWM modes(Center aligned vs edge aligned ) will impact performances, assuming that both MOSFETs will be driven with the same duty cycle(regulated by a PID / PD loop on output voltage), but 90 degrees apart?

And I need to put flyback diodes in parallel with the n-MOS?

Thanks in advance.

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  • \$\begingroup\$ V=4.44*N1*f*Bmax is only valid for sinusodial forward-type converters, which yours isn’t. Use Vt=NAB instead. \$\endgroup\$ – winny May 2 '19 at 16:47
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    \$\begingroup\$ Just a point : Your R1 carries no current. \$\endgroup\$ – Marla May 2 '19 at 16:50
  • \$\begingroup\$ @Marla, ops I drew it wrong \$\endgroup\$ – Blu eyes May 2 '19 at 16:52
  • \$\begingroup\$ @winny thank, for your answer, but the A for what stand for? \$\endgroup\$ – Blu eyes May 2 '19 at 16:54
  • \$\begingroup\$ A is core Area, but @winny could it be this? $$N_{s}A_{c}∆B_{m}= {L∆I_{m}}{}$$ \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 2 '19 at 18:24
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Core loss factors that may not depend on frequency are :

Core eddy current loss is a function of the volts per turn applied to the windings, and the duty cycle. It can be modelled by placing a resistor across one of the windings. According to "Magnetics Design for Switching Power Supplies" *1 by Lloyd H. Dixon, eddy current losses start to become significant > 200KHz and I believe that depends on better core material choices with lower permeability and higher core conductance.

  • For example, a square wave of 5 Volts/turn, applied to the primary, will result in the same eddy current loss regardless of frequency.

Hysteresis losses increase with frequency.

For acceptable losses, flux density swing ΔB must be restricted to much less than \$B_{SAT}\$. This prevents the core from being utilized to its full capability but provides a safety margin to thermal runaway when L drops to 0 when saturated.

Core loss is usually expressed in mW/cm³.

e.g. Ref *1 p15 of 84 enter image description here

ΔB, is calculated from Faraday's Law $$Volt-sec=N_{turns}\cdot A_e \cdot ΔB =LΔI $$ for N turns, and Ae cross-sect. area

At a fixed switching frequency and with the normal steady-state operation, the volt-seconds applied to the transformer windings are constant, independent of line voltage or load current. So for a forward rectified converter, the duty cycle must be limited to 50% to allow for core reset.

Your schematic is for a push-pull centre-tap converter. Here you can go up to 100% duty cycle but in a practical sense, since spectral energy bandwidth, BW increases away from 50% duty cycle operating above 90% increases hysteretic losses more.

Conclusion

Choosing the optimum operating frequency depends on power losses at 90% duty cycle at the chosen core loss levels and find the frequency where it starts to increase quadratically as opposed to linear loss rise with f at max duty cycle (e.g. 90%) which has a fundamental 1st null at 10x f. These harmonics may interfere with parallel resonant frequency SRF which is well above the switching rate so awareness of this effect, I encourage you to examine the output spectrum or with careful probing to avoid probe resonance >10MHz and measurement error, detect the ringing due to the core LC load effects by monitoring the DC current while observing the waveform.

Flux walking is not a problem with the forward converter if the primary off FET switch has an adequate Zener to decrease the magnetizing current to 0 in time ΔT.

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  • \$\begingroup\$ any questions ? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 3 '19 at 3:01
  • \$\begingroup\$ I didn't understand where place the zener diode. \$\endgroup\$ – Blu eyes May 3 '19 at 6:04
  • \$\begingroup\$ So if understood correctly, I need to increase frequency measuring the losses and watching the DC current(to prevent ringing due armonics), when the losses start to increases quadratically. The transformer must be driven without load? \$\endgroup\$ – Blu eyes May 3 '19 at 6:07
  • \$\begingroup\$ How frequency affect maximum current/power that can be pulled of the transformer. Increasing frequency, with the same steady-state currenyt will saturate the core more quickly? \$\endgroup\$ – Blu eyes May 3 '19 at 6:10
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You're asking a lot but I can at least answer part of it. Optimal switching frequency for a transformer is typically governed by the parasitic capacitance. If you can measure the Self-resonant frequency or distributed capacitance (example method) then you know that you need to stay well below that frequency.

In regards to how switching frequency affects the performance, increasing frequency typically allows you to achieve the sample ripple with smaller value components but those components need to be functional at the higher frequency. So increasing the frequency won't necessarily improve performance if you are operating near or above the capacitors' critical frequency.

It would be good practice to use flyback diodes or a snubber circuit to protect the transistors.

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    \$\begingroup\$ Faster switching also increases core and AC loss, which might be more of a limiting factor than the parasitic capacitance or self-resonant frequency. \$\endgroup\$ – John D May 2 '19 at 17:24
  • \$\begingroup\$ So, If I understand correctly the frequency needs to be a way lower than the self-resonant one, lower than the capacitor critical frequency and must allow the mos to full turn on and off. Can I find this with the trial/error method, ie sweeping through the frequency spectrum and picking the one that offers the maximum efficiency, or there's a more concrete/theoretical method? \$\endgroup\$ – Blu eyes May 2 '19 at 17:34
  • \$\begingroup\$ @Blueyes There are concrete methods to find SRF like the one I cited in the answer. However, they might depend on what equipment you have to test with. The capacitor critical frequency is typically given on the data sheet though. \$\endgroup\$ – Oscillonoscope May 2 '19 at 17:39
  • \$\begingroup\$ @Oscillonoscope, I understand how to measure the SFR, having access to a signal generator and an oscilloscope this should be feasible, I don't understand how chose the right frequency. For example, assuming that I measured the SFR of my transformer, let's call it X, now assuming that I'm far below the limit of the switching device, that the critical frequency of the capacitor is Y and that the minimum switching frequency is W, what is the optimal frequency in the range (W<->min(Y;X/k)), where k>1 is a factor to "decide" the "safe area" below SFR; \$\endgroup\$ – Blu eyes May 2 '19 at 18:02

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