I need confirmation that the following circuit diagrams are correct for their Boolean expressions. I've been told that each logic circuit must have a MAXIMUM of 4 NAND gates, however, I cannot manage any less than 5. Thanks in advance.enter image description here

  • \$\begingroup\$ Good start. Can you draw the Boolean diagram too? \$\endgroup\$
    – winny
    May 25 '19 at 13:44
  • \$\begingroup\$ By that do you mean the truth table? \$\endgroup\$
    – Patrick
    May 25 '19 at 13:48
  • \$\begingroup\$ Sorry, wrong guy! Karnaugh diagram! \$\endgroup\$
    – winny
    May 25 '19 at 15:09
  • \$\begingroup\$ Do you know yet the fundamental laws in logic? distribution, de Morgan, etc. If not , why not? \$\endgroup\$ May 25 '19 at 20:21

Let me put across how I'd go about the first one and leave the second one to you. Since there is an already simplified expression in your case i.e (no further simplification possible using laws of boolean algebra), the only way around in such cases to look at optimization of gates using an alternative implementation, which can be done by taking a double negation (since NAND is required) over the entire expression and solving it using De Morgan's law. In this case that would be to reuse the input A to reduce a few gates.

I made the circuit using circuit verse which you can check out here. You can also simulate with any permutation of inputs there.Please let me know if this answers your question.

Hint for the second one: It must be safe to assume that negated C is already available as a direct input by estimating the least number of gates using the above method.

Simplification for both the above cases reference: Simplification

  • \$\begingroup\$ Thanks for your answer, yes it helped me. \$\endgroup\$
    – Patrick
    May 26 '19 at 6:55
  • \$\begingroup\$ Thanks for the update! You can mark it as accepted (the tick mark below the upvote/downvote button on the left hand side) in case you have no further questions regarding this so that the question can be marked answered. \$\endgroup\$ May 26 '19 at 10:57

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