Consider the following. Let's say for simplicity sake I have an arrangement of 8 bit registers in a 4x4 matrix layout. I could easily use a Demux that has a 4 bit input select line for the addresses with an 8 bit data input and from that address line I can then easily select which of the 16 registers I want to access.

Instead of using a single Demux let's say I want to use 2 Demuxes to do the same thing except I want to designate one Demux to represent which row and another to represent which column.

I'll still be using the same 4 bit address line only I was thinking of using a wire splitter and using the 2 lower order bits of the address line for one demux and the two higher order bits of the address line for the other.

How would I be able to set up the arrangement of these Demuxes to access the appropriate row and columns of my matrix arrangement of registers?

Do I need to feed the data line into both demuxes? Would I need addition logic or muxes to combine the two lines? Or would a decoder help in this kind of situation? This is where I'm getting stuck at in my design decision.

I could use a single Demux however due to the limitations of Logisim my actual registers are 32 bits each and I have an arrangement of 8x8 registers for a total of 64 registers. I'm planning on using this as Cache for my CPU instruction register or instruction decoder.

If you need any more information than this or need any kind of diagrams or images let me know and I'll upload - post them upon request.

Here's my 16x1 byte register arrangement using a single Demux: 16x1 Register

I want to make something similar however it won't be 4x4 as it will be 8x8 and the registers won't be 8 bits as they will be 32 bits and I was planning on using 2 Demuxes one for the row and the other for the column.

  • \$\begingroup\$ Can't you just use 3-state registers? \$\endgroup\$
    – Finbarr
    Aug 25, 2019 at 15:23
  • \$\begingroup\$ @Finbarr Not sure exactly what you are asking; I'm using Logisim's built in registers... I'm then adding tri state logic to their outputs. They each have a load and a clear line as well. \$\endgroup\$ Aug 25, 2019 at 15:26
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    \$\begingroup\$ I don't understand why you're adding 3-state outputs and then multiplexing them anyway. \$\endgroup\$
    – Finbarr
    Aug 25, 2019 at 15:33
  • \$\begingroup\$ @Finbarr by default the output is enable because it is active low. If you set the enable line high it will completely disconnect the output from the bus line. I have to do it this way because of the limitations within Logisim. Logisim doesn't have any easy way to simulate a bus line that can act as bidirectional. So if I'm feeding information off of a bus line from both input and output onto the same line I have to add this mechanism to disable or disconnect the output completely. This is why I am adding the 3 state logic to the output of my registers; otherwise I wouldn't need to. \$\endgroup\$ Aug 25, 2019 at 15:41
  • \$\begingroup\$ @Finbarr The multiplexing is to select which register I want from the address line that is all the multiplexing is doing. Once I have the register I want to use, it then has a 3 bit control line. One to load data into the register (write operation), one to enable or disable the output( read operation ), and a clear or resent operation. The demux is only to select which register is in current use. \$\endgroup\$ Aug 25, 2019 at 15:47

2 Answers 2


You can not do what you want with just 2 MUXes. For your example, you might use one 4:1, 8-bit, MUX for each row to select the register from one column in this row. A fifth 4:1 MUX selects the output from one of the rows.

That's a lot of multiplexers, which is why we typically use a multiplexed data bus for a register array. Every register has 3-state outputs and the selection logic allows only one register's output drivers to be active at any point in time. Then you can just connect the data outputs of all of the registers together

  • \$\begingroup\$ I appreciate the feedback; I think I understand what you are saying. Just take into consideration that I'm purely self taught and I've only been learning about hardware construction at the gate levels for only the past couple of months. I'm diving this deep into the abstraction levels to get a better understanding of how a CPU is designed and how Assembly Code and Op codes work with a specified architecture, platform or framework this way when I go back to working in C/C++ I'll have a much better understanding of how the compilers are treating the C/C++ code to generate translation units. \$\endgroup\$ Aug 25, 2019 at 17:06
  • \$\begingroup\$ So would it be just better to use a single Demux then and have 6 select bits? I'm not sure of the limitations of Logisism with this approach. \$\endgroup\$ Aug 25, 2019 at 17:09
  • \$\begingroup\$ Or instead of using a demux to send the 32 bits to the 64 registers, just have the data line go to all of them and use a demux for the control lines? \$\endgroup\$ Aug 25, 2019 at 17:14
  • \$\begingroup\$ The issue here is that within Logisim I can only have 5 select lines for a demux and not 6. \$\endgroup\$ Aug 25, 2019 at 17:17

I’m going to assume for the moment you have some specific reason to need an array of registers with all of their bits available. If this isn’t the case this function should look more like a RAM and would be more compact if implemented that way.

You can use two layers of 8-bit 4:1 muxes for a 4x4 matrix. One layer selects column, the other layer selects row. This is how it would be implemented in an FPGA if you need a register array, as FPGAs don’t tend to have support for 3-state buses.

You can also build muxes from 3-state buffers. This is roughly the same complexity as using the layered muxes, but would be easier to route in layout as a physical design.

  • \$\begingroup\$ Thank you for the answer. I'm a bit new to this; been studying it for a couple of months now. Catching on pretty quick. All of the individual parts I can make from logic gates such as muxes, registers, alu, etc. I'm just struggling a little bit with the control logic and putting them all together. Trying to build a 32 bit cpu in Logisim. I was thinking of making 64 x 4byte registers to act as cpu cache. It would on a bus, but it would be an internal cpu bus, not an outside I/O bus. I was planning on using it for the PC, IR, MAR and SP. I was thinking of having another just for the ALU too. \$\endgroup\$ Aug 26, 2019 at 4:09
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    \$\begingroup\$ You might also be interested in the idea of multiple read ports. A 2-read 1-write would double up the number of muxes, but you get two operands at the same time. This is what a 'register file' does, and it's a common feature in CPU design. \$\endgroup\$ Aug 26, 2019 at 20:20
  • \$\begingroup\$ I'll have to check that out. I'm at the stage where I'm starting to connect the dots between modules and constructing or setting up the data paths and control logic... \$\endgroup\$ Aug 26, 2019 at 20:24

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