I am thinking to go in for a FPGA starter kit, I browsed the Xilinx website and found that the Spartan 3 series were quite economical - Spartan3AN, Spartan3A and Spartan3E. The Spartan 3AN seems to be a new board.
Can the Spartan FPGA handle processing of a 5MegaPixel camera, interface would be 8bit parallel data in raw rgb, and do some edge detection 15 times a second?
In terms of interfacing to the camera and clocking data in, that will be fine it can handle it. It may not handle the speeds you are interested in.
5MP * 3 (colours, RGB) * 15 (times per second) = 225*e6. (assuming 24 bit colour depth)
So that means you will need a clock speed of at least 225 MHz assuming you can move data on every clock signal, which you may not, depending on the sensor, so you may need to double this figure to circa 450-500 MHz
The Spartan you are looking at has a clock signal of 50MHz.
So the short answer is no, not at those speeds.
The other consideration you need to apply is how many logic blocks does your logic require? to work this out, write out your implementation in VHDL/verilog, simulate and then synthese. Read the outputs from the tool and it will tell you how many logic blocks you need, then select an appropriate FPGA which has 50% more logic blocks to allow for unuseable blocks due to routing constraints and gives you some room to grow.
Also you need to consider RAM or some other sort of memory and how your will store these bursts. If you are shooting at 15 fps for 1 second then you need 225 MB which is a lot or RAM for an embedded system.
After storing in RAM you will need to flush into ROM of some sort (for example compact flash).
We simply don't know enough from the question and comments (as yet). Internally a Spartan 3 family chip could probably do the edge detection, but reading the image sensor at that speed is more of an open question - it depends more on the sensor interface and board layout. Then there's the question of what to do with all the data - it's doable to just feed it out again, possibly using wider connections, but the FPGA itself certainly can't store it.
Unfortunately this question is turning into more of a discussion, which this site wasn't designed for. We keep having to dig to find the new comments. To give a verifiably correct answer, we would have to do half the design work - all the way to component selection and algorithm data flow.
