I am thinking to go in for a FPGA starter kit, I browsed the Xilinx website and found that the Spartan 3 series were quite economical - Spartan3AN, Spartan3A and Spartan3E. The Spartan 3AN seems to be a new board.

Can the Spartan FPGA handle processing of a 5MegaPixel camera, interface would be 8bit parallel data in raw rgb, and do some edge detection 15 times a second?

  • \$\begingroup\$ Might take some work, but yes, should work. \$\endgroup\$
    – Kellenjb
    Oct 7, 2010 at 14:52
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    \$\begingroup\$ @Kevin Boyd - That depends on your algorithm. \$\endgroup\$ Oct 15, 2010 at 18:38
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    \$\begingroup\$ Basically, this question is impossible to answer. MUCH more detail is needed. Fundamentally, it won't be possible to provide a conclusive answer until you have actually written the edge-detection algorithm. That is the only way to determine how many logic elements you need for your design, and therefore how big of an FPGA you need. \$\endgroup\$ Oct 15, 2010 at 18:39
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    \$\begingroup\$ Furthermore, do you really need the 5 mpix? In many industrial CV applications, the actual processing is done on a heavily downscaled (~200x200 px images) images, because any more precision is simply unnecessary. Now much precision do you need? Also, the imagedata is going to be flattened to at least greyscale, and likely pure B&W (perhaps with an adaptive threshold) prior to processing. Therefore, are you doing something clever with color, which requires a RGB camera, or would a greyscale camera, perhaps with a color filter on the lens work? \$\endgroup\$ Oct 15, 2010 at 18:45
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    \$\begingroup\$ en.wikipedia.org/wiki/Edge_detection is a good place to start for understanding how this stuff works \$\endgroup\$ Oct 15, 2010 at 18:47

2 Answers 2


In terms of interfacing to the camera and clocking data in, that will be fine it can handle it. It may not handle the speeds you are interested in.

5MP * 3 (colours, RGB) * 15 (times per second) = 225*e6. (assuming 24 bit colour depth)

So that means you will need a clock speed of at least 225 MHz assuming you can move data on every clock signal, which you may not, depending on the sensor, so you may need to double this figure to circa 450-500 MHz

The Spartan you are looking at has a clock signal of 50MHz.

So the short answer is no, not at those speeds.

The other consideration you need to apply is how many logic blocks does your logic require? to work this out, write out your implementation in VHDL/verilog, simulate and then synthese. Read the outputs from the tool and it will tell you how many logic blocks you need, then select an appropriate FPGA which has 50% more logic blocks to allow for unuseable blocks due to routing constraints and gives you some room to grow.

Also you need to consider RAM or some other sort of memory and how your will store these bursts. If you are shooting at 15 fps for 1 second then you need 225 MB which is a lot or RAM for an embedded system.

After storing in RAM you will need to flush into ROM of some sort (for example compact flash).

  • \$\begingroup\$ 50MHz oscillator - the PLLs can bring the FPGA much higher. And the 3A Starter comes with a 133MHz oscillator to feed its DDR2 ports. So it could do the I/O, but it depends on more design aspects. Depending on the algorithm, the 3A DSP may do better. \$\endgroup\$ Oct 16, 2010 at 13:27
  • \$\begingroup\$ you are right about the PLL and running it faster, that will be possible. However it may not be fast enough still for the amount of data that needs to be transferred in, also there is not enough in built RAM within the device, less than 2MB and the development kit has support for 64MB, which is not enough. \$\endgroup\$ Oct 16, 2010 at 21:03
  • \$\begingroup\$ So we're back at depends on the algorithm. An edge detection algorithm could possibly get away with only a few scanlines of memory, but that's assuming it outputs the data with very little delay as well. Kevin Boyd has not indicated that recording is necessary nor any additional details. I figure not enough information, still. \$\endgroup\$ Oct 17, 2010 at 12:59
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    \$\begingroup\$ It can be clocked higher externally, and isn't limimted to 133MHz either - that's just what the second external oscillator on the 3A Starter board uses. Limits depend on logic complexity, but pipelining can push them quite high. The real question is still more what to do with the data after reading it. You certainly can connect to any amount of RAM, but eventually you'll want to use the data somewhere. \$\endgroup\$ Oct 19, 2010 at 11:04
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    \$\begingroup\$ Remember you will also need to put an SDRAM/SDR/DDR/DDR2 controller in the FPGA as well... \$\endgroup\$
    – akohlsmith
    Oct 19, 2010 at 11:24

We simply don't know enough from the question and comments (as yet). Internally a Spartan 3 family chip could probably do the edge detection, but reading the image sensor at that speed is more of an open question - it depends more on the sensor interface and board layout. Then there's the question of what to do with all the data - it's doable to just feed it out again, possibly using wider connections, but the FPGA itself certainly can't store it.

Unfortunately this question is turning into more of a discussion, which this site wasn't designed for. We keep having to dig to find the new comments. To give a verifiably correct answer, we would have to do half the design work - all the way to component selection and algorithm data flow.

  • \$\begingroup\$ Is there anything wrong with having discussion on this forum? I understand the intent may be to have questions and answers to draw in more users and traffic, but discussing the technical details is still helping the OP to work through their solution. I am sure if the OP was able to answer all of the extra questions posed, they would not be asking anything on this forum, as the answer would have come out in the design process. just some thoughts .... \$\endgroup\$ Oct 19, 2010 at 11:44
  • \$\begingroup\$ Nothing wrong with discussion as such - just the layout isn't very good at it. There appear to be plans to add the function (Chat function under reputation), but it's not ready yet. I would have linked it but it seems to be in closed beta. electronics.stackexchange.com/privileges/chat-rooms \$\endgroup\$ Oct 19, 2010 at 14:37

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