I already know how Gate-bias, Self-bias, and Current-source bias works in a JFET configuration. However, I am still stuck in voltage-divider-bias JFET circuit. (circuit below)
In a JFET circuit, the gate-source voltage must be reverse-biased. However, in a VDB JFET circuit, the gate voltage is always positive.
Posted below is also the transconductance curve, it shows that the Q point in this VDB circuit will have a negative voltage at either Q1 or Q2, how is that suppose to happen if VDB produce positive voltage at the gate?