How to build a true ultra low power binary counter

Question

I'm looking for a true ultra low power binary counter of ~10 bits (can be longer) The frequency is not important, I will count pulses, almost static events but I need 10uA max. at 3V

This one for example can be ok at 25deg (with 4uA) but at higher temperature can reach 40uA which is 10x worse than normal. https://toshiba.semicon-storage.com/info/docget.jsp?did=15759&prodName=74VHC4040FT

Another idea (taken from here I believe) is to use some cascaded D-flips (74AUP series) like this one https://assets.nexperia.com/documents/data-sheet/74AUP1G74.pdf

But will be 0.9uA per device x 10 bits = 9uA (over temp) + additional cap. loading. This is the most pro missing solution I found so far.

I'm curios if there is other way to build it.

Thank you in advance,

Answer 1

If you're really worried about power consumption you probably have two routes:

1) An FPGA/CPLD-like thing

The Dialog Semiconductor nee Silego GreenPAK stuff has counters built into the fabric. You probably can't beat it with anything discrete as it has about 1uA of quiescent current. Your power consumption will be defined by frequency.

https://www.dialog-semiconductor.com/products/slg46127

2) A microcontroller

Most microcontrollers have counters and interrupts built to trigger off their GPIOs and wake the microcontroller up on a pulse or edge. Some of them may even be able to stay asleep and still run the counter circuitry.

The Ambiq micro stuff is 10uA/MHz. So, if you run at 1MHz or less, you hit your numbers. https://ambiqmicro.com/mcu/

However, if you can find a micro that lets your microcontroller sleep and still count, you can probably beat that quite easily.

Hope this helps.

Answer 2

CMOS logic will be low power, or you have a bad design or flawed silicon process.

Select a counter (or FFs) with low Iddq at +5 volts, and the Iddq will be even lower at +3.3volts

However, you need to provide FAST edges into that counter, or the do_we_change_state_now transistors will burn lots of power near the trip point.

So I suggest you concern yourself with the input-pulse-shaping circuit Iddq, or the external sensor that provides the pulse.

CMOS logic, using both Pchan and Nchan, are silicon-leakage-limited in their static operation. If the silicon designer used the shortest-allowed dimensions (for the fastest speed), then the Iddq may be detectably non-zero; avoid those product lines.

However, even static CMOS requires the input "logic" levels be at your rails (gnd or VDD) or all bets are off regarding the Iddq.

This concern again points to requirement about the input "pulse" --- it must remain at the rails at all times unless moving in a VERY FAST risetime or falltime.

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I view each CMOS gate as a 100 microAmp shoot_through generator. I view each flipflop as a 2,000 microAmp shoot_through generator. A 10 FF counter will be 20,000 microAmp shoot_thru generator.

A clocking event of 1 nanosecond duration consumes

• Q == I * T

• Q == 20,000uA * 1nanoSecond == 20,000 femtoCoulomb == 20 picoCoulombs

• Q == 20e-12 Coulombs, or 20 picoAmperes at ONE PULSE PER SECOND

but if your clocking system is SLOW EDGED, and if all 10 FFs are exposed to that SLOW EDGE clock transient, your "Iddq" soars.

Regarding that pulse conditioner: I suggest a very low current amplifier, perhaps 1Meg ohm along with Cparasitic of 10 picoFarads; this may guarantee a 10 microsecond edge speed.

Then follow that with a SCHMITT TRIGGER that uses long_channel FETs, so its shoot_through current can be low as the transistors linger within the linear region. You may need to characterize various versions of IC_schmitts, testing them with SLOW triangle-shaped input waveforms that are not quite at the rails; use 0.2v to 3.1 volts, not 0.0 to 3.3volts.