UPDATE: The issue with debugging someone else's code is you just have to assume everything is being coded correctly. I just checked datasheet and there was this BSY (bus busy) flag bit in status register. I just made it so that it waits for BSY bit to get reset and now the ~CS behaves properly. Sorry.
Working on TIVA-C 123GH6PM. Sending data over SPI lines does not produce the desired result. I am sending 3 bytes of data in one ~CS cycle and using the Freescale frame format. The ~CS line goes high before sending the last byte.
If I send 2 bytes of data, the same thing occurs - the last ~CS goes high before I have the 8 clock cycles.
The only workaround I found was adding some delay before pulling ~CS high or sending another byte of data which of course doesn't get sent.
This is my write subroutine :
void SPI_write(uint8_t data)
{
*(__IO uint8_t *)&SSI2->DR = (uint8_t)data;
while((SSI2->SR & (1<<0))==0);
}
I tried type casting as you see above as I have worked on STM32 before and that has data packing, and typecasting there pulls ~CS properly, just as a last ditch effort.
Why does the ~CS line behave so strange? Is there a proper solution to solve this?
PS: I have selected the data size to be 8 bits just in case that comes out as a suspicion. If the full code is needed, I shall update the post with it,, just let me know
SSI2->SR & (1<<0)? \$\endgroup\$