Power measurement on multiple loads

Question

I'm designing a circuit for driving multiple loads (min. 16, up to 64) like the one shown below

^{simulate this circuit – Schematic created using CircuitLab}

The input source is from a multi-channel DAC driven by an ATMega-like uC that can range from 0 to 5 V, and it should be able to generate a sawtooth with a minimum frequency of 1 kHz. As for the maximum frequency, this will be a trade-off between the resolution and speed of the scan. With this design, the circuit should be able to provide up to 50 mA to the load. The load resistance can vary from 100 to 3000 Ohm.

The problem is, I need to know accurately how much power is delivered to the load and I have a tight requirement of max 100 mW for each. For this reason, I'd like to introduce a monitor on the voltage using a multi-channel ADC and send it back to the uC. In this way, besides having a power monitor, I'd have a closed-loop feedback for better control. However, I'm afraid that placing the monitor in this way would cause a number of issues:

1. (minor) Output resistance of the current source would be affected by the monitor (e.g. using a voltage divider before the ADC)
2. (major) Need to share the SPI bus between the DAC and the ADC, lowering the maximum frequency I can obtain.

Before considering another uC, do you have any suggestion on how you would implement such functionality? Would you also consider the possibility to disable the monitoring for open-loop control?

Answer 1

If you do use this type of schematic from TI it should work (on a more limited power supply): -

In the comments below the question I explained why the proposed circuit won't work (take note of op-amp type and the components in the orange boxes in my schematic). Those boxed components will certainly be needed if R3 is going to be as low as 10 Ω.

Also take note that the TI design uses an OPA2376 op-amp and this limits the power supply to no-more than 5.5 volts. You need to find a rail-to-rail op-amp that has decent spec and can operate from a 20 volt supply (as per the faulty diagram in the question).

I added a few notes and basically, if you monitor V(R1) and you have accurate resistors you can reliably predict load current: -

$$I_{OUT} = \dfrac{V(R_1)}{R_1}\times\dfrac{R_2}{R_3}$$

Use a high impedance voltage monitor circuit to measure this voltage. A 1 MΩ input impedance will degrade R1 to a 0.5% lower value for instance. I'd go for at least 10 MΩ input impedance for the monitor on R1 in my schematic.

For the output voltage monitor, keep with an input impedance of 10 MΩ or greater.

Need to share the SPI bus between the DAC and the ADC, lowering the maximum frequency I can obtain.

That's something that cannot be answered here.

Would you also consider the possibility to disable the monitoring for open-loop control?

That's up to you. Adding a few bells and whistles is always a good thing to do at an early stage rather than try and bodge in something later on.

It's almost imperative that you use a simulator to test this before committing to a PCB layout.