capacitance at inverting op-amp input of unity gain inverting amplifier

Question

[This question is related to another question. That other question asks why a particular op-amp behaves the way it does. I think there are many reasons, many of which are outlined in the answers to that question. However, there is one reason that I think is not a significant contributor to the op-amp's behavior, and that is capacitance on the inverting input of the op-amp. Since I don't have a full explanation/answer to that particular question, I have created this question, to clarify (hopefully) one particular issue.]

In a particular op-amp circuit, it was observed that multiplying all of the resistor values in that circuit by a constant altered the frequency response to that circuit. Although the circuit was presented as a unity gain differential amplifier, the non-inverting input was held at ground potential. So, here, I have simplified the circuit to a unity gain inverting amplifier:

^{simulate this circuit – Schematic created using CircuitLab}

Using the CircuitLab model, I was not able to reproduce a change in frequency response by changing the resistors from 100k\$\Omega\$ to 100M\$\Omega\$. However, changing the resistor values to 100\$\Omega\$ did make a change to the frequency response. I believe the spice model used by the poster in the aforementioned question is more sophisticated than the CircuitLab model. However, the element that I want to model, namely input capacitance, shows some characteristics that should be present regardless.

The model which I wish to consider is this:

^{simulate this circuit}

The frequency response of this circuit looks like this:

I have simulated this circuit with multiple different resistor values, multiple different capacitor values, and multiple different op-amps. In all cases that I tested, there is a characteristic peak in amplitude, followed by a rolloff of about 40 dB/decade. At the peak frequency, there is a characteristic phase change of 180-degrees. (or in the case of very low resistor values, a phase change of a multiple of 180-degrees).

[Note that the peak frequency is not the break-frequency of a standard RC low-pass filter. Changing the resistor or capacitor values by a factor of 10, changes the peak frequency by a factor somewhere around 3, but the factor changes a bit, and is not exactly the square root of 10. I would offer that the characteristics are those of a complex conjugate pole pair.]

The characteristics that show up in my modeling, are in agreement with the described effects of input capacitance on the inverting (negative) input of an inverting amplifier in this TI application report on the effects of parasitic capacitance on op-amp circuits.

Now, please compare what has been seen above with the frequency response in the prior question.

This response was taken when the resistors were set a 100M\$\Omega\$.

My question, is whether it is reasonable to conclude from the absence of an amplitude peak, and the sudden 180-degree phase shift, (characteristic of capacitance at the inverting input of the op-amp,) that such parasitic capacitance at the op-amp input plays a negligible role in the frequency response observed in the circuit which lacks the explicit capacitor? Perhaps I am missing something.

Edit: Perhaps I could put my question in another way. Some factor or factors cause the bandwidth of the op-amp circuits to be limited. One possible limiting factor is the input capacitance together with the circuit resistors. However, when bandwidth is limited by input capacitance combined with circuit resistors in models, the models show tell-tale signs, especially an amplitude peak and a sudden 180-degree phase reversal. If the frequency response of a circuit does not appear to have these features, is it reasonable to conclude that some other factor or factors are limiting the bandwidth? Is it reasonable to conclude that, although the input capacitance may play some role in the frequency response, it does not play the dominant role? Or would that reasoning be faulty?

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Information for @AndyAka

Here is the frequency response with the resistors both set to 100\$\Omega\$, and no capacitor at the input.

Notice that the 3dB cutoff frequency is around 500kHz, and notice the 90 degree phase shift.

Now here is the frequency response with 100M\$\Omega\$ resistors and a 100 pF input capacitor.

Notice the peak at about 4kHz and the 180 phase shift.

Next is the frequency response with 100M\$\Omega\$ resistors and a 100 fF input capacitor.

The peak has moved to about 150 kHz. It is wider and with less amplitude, but still quite noticeable.

Even with the capacitor at 10fF (and the resistors at 100M\$\Omega\$), the "peak", though quite wide and not very tall, is still discernible as is the 180 degree phase shift.

The peak here is almost at the 500kHz -3dB bandwidth found earlier. If the capacitance is made even smaller, the "peak" will disappear into the roll-off caused by the op-amp's internal compensation capacitor.

With smaller resistors, the same sequence is observed, except at different capacitance values.

Now in the next graph, there is NO observable peak.

There is a roll-off with a break frequency of around 15kHz. I do not doubt that this initial roll-off is due to capacitance somewhere in the op-amp. However, the absence of a peak suggests to me that the capacitance that is causing the roll-off is likely elsewhere than at the inverting input. [Looking at the phase plot, it looks to me like there may be a second pole between 100kHz and 500kHz. I wouldn't be surprised to learn that this higher frequency break is caused by capacitance at the inverting input.]

Perhaps I am wrong in my hypothesis, but I have not seen the "peak" disappear except into the high frequency roll-off which is generated by the op-amp's compensation capacitor. So, if there is something that suggests my guess is wrong, I am still unaware of it.

Answer 1

TL;DR - the LM324's output stage distortion is screwing up the behavior vs the model with R1=R2=100k, C1=1nF. If Rload=1K to Vee is added, it then matches the CircuitLab model (and also a 1-term algebraic model). With no cap and no load, other things inside the op-amp seem to add a delay of a couple hundred ns to the -1 gain configuration.

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Will begin by working through a 1-term algebraic model.

Simplified model of the op-amp gain:

• Let \$\omega_A=2\pi(GBW)\$
• Let \$A_{OL}=\omega_A/j\omega\$

Then,

• Let \$V_i,V_o,V_N\$ be the voltage at input, output, and inverting terminal
• Let \$Z_1,Z_2,Z_3\$ represent \$R_1,R_2,C_1\$, just to start out

The voltage at the OP amp's inverting input is

$$V_N= \frac{(V_i){Z_2}{Z_3}+(V_o){Z_1}{Z_3}+(0){Z_1}{Z_2}}{{Z_1}{Z_2}+{Z_1}{Z_3}+{Z_2}{Z_3}}$$ And the output is $$V_o = -{A_{OL}}{V_N}$$ From this, if I didn't screw up the algebra, I get $$\frac{V_o}{V_i} = \frac{-1}{\frac{Z_1}{Z_2} + \frac{1}{A_{OL}}(1+\frac{Z_1}{Z_2}+\frac{Z_1}{Z_3})}$$

Substituting the symbols from the original circuit

$$\frac{V_o}{V_i} = \frac{-1}{\frac{R_1}{R_2} + \frac{j\omega}{\omega_A}(1+\frac{R_1}{R_2}+j{\omega}{R_1}{C_1})}$$

$$\frac{V_o}{V_i} = \frac{-1}{\frac{R_1}{R_2} + ({j\omega})(\frac{1+{R_1}/{R_2}}{\omega_A})+(j\omega)^2(\frac{{R_1}{C_1}}{\omega_A})}$$

Using \$R_1=R_2=100k\$ ; \$C_1=1n\$ ; \$\omega_A=2{\pi}(1MHz)=6.3M\$

$$\frac{V_o}{V_i} = \frac{-1}{1 + ({j\omega})(\frac{2}{6.3M})+(j\omega)^2(\frac{0.0001}{6.3M})}$$

Which comes out like this in Octave/Matlab (CORRECTED):

s=tf('s'); wa=2*pi*1e6; bode( -1/(1 + s*2/wa + s^2*0.0001/wa) )

Note radians on the horizontal axis.

So this looks a lot like the graph of the first model (CircuitLab?) in the OP question. The 40 dB/decade is coming from the two-pole response, and the abrupt -180 phase is from the resonance. I don't know what's going on in that Spice model.

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UPDATE1 - So this was bothering me. I built a test circuit during a long zoom session.

Here is the result with R1=R2=100k, no cap, no load.

Next, here is R1=R2=100k, with 1.5K R_load added to GND. Also used a smaller input with 51ohm termination.

Next is same but R1=R2=10k. (I also did R1=R2=1k but it did not change much from this).

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UPDATE2 - I then tried connecting Rload=1k from Output-to-Vee, instead of Output-to-GND. This did not change the results without C1 cap much (shaved another 25ns off the delay). But it made a big difference once C1 was added (below).

It seems this was because of the output stage again. With Vin = 100mVpp -150mVoffset (i.e. output DC level = +150mVdc), Rload going to GND became ineffective at preventing output stage distortion after there was some positive gain. It caused an asymmetrical waveform and a hysteresis behavior, where the peak freq moved about 20-25% depending on whether the frequency was rising or falling. Rload going to Vee fixed it. It also turns on the output quite a bit more (10mA DC).

So with an Rload added to make the output stage behave, and adding C1, it then becomes pretty close (for <100kHz) to the CircuitLab model and the 1-term algebraic model at the top of this answer!

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UPDATE3 - lastly, what would the algebraic model look like if a delay was added to the A_OL expression above?

The following 3 graphs show it. I reduced the GBW to make it line up with measurements when R1=R2=100k. The delay values are also picked to line up with variations from the output load conditions described above.

The following graphs are calucluated, using ideal algebraic model with delay.

So the tentative conclusion is that the larger R1=R2=100k reduces GBW a little bit, and output conditions alter delay a little bit. This seems to extend the model out from 100Kish to 500Kish.

I suspect more modern op-amps don't have these issues in ordinary cases, since the LM324 is nearly 50 years old, and process of that time used fairly slow transistors on the IC.